cs4239 Cirrus Logic, Inc., cs4239 Datasheet - Page 42

• Manufacturer Part Number: cs4239
• Description: Crystalclear? Ortable Isa Audio System Logic
• Manufacturer: Cirrus Logic, Inc.

DIV5 - DIV0
SRE
Extended Register Access (I23)
Default = xxxxxxxx
XA4
XRAE
XA3-XA0
42
XA3
D7
XA2
D6
XA1
D5
Clock Divider. These bits select the
audio sample frequency for both cap-
ture and playback. These bits can
be overridden by IFSE in X11.
Fs = (2*XT)/(M*N)
XT = 24.576 MHz
XT = 16.9344 MHz CS2 = 1
N = DIV5-DIV0
16
12
(M set by OSM1,0 in I10)
M = 64 for Fs > 24 kHz
M = 128 for 12 kHz < Fs
M = 256 for Fs
Alternate Sample Rate Enable. When
this bit is set to a one, bits 0-3 of I8
will be ignored, and the sample fre-
quency is then determined by CS2,
DIV5-DIV0, and the oversampling
mode bits OSM1, OSM0 in I10. Note
that this register can be overridden
(disabled) by IFSE in X11.
Extended Register Address bit 4.
Along with XA3-XA0, enables ac-
cess to extended registers X16
through X31. MODE 3 only.
Extended Register Access Enable.
Setting this bit converts this register
from the extended address register
to the extended data register. To con-
vert back to an address register, R0
must be written. MODE 3 only.
with XA4, sets the register number
(X0-X31) accessed when XRAE is
set. MODE 3 only. See the WSS Ex-
tended Register section for more
details.
Extended Register Address. Along
XA0
D4
N
N
49 for XT = 24.576 MHz
33 for XT = 16.9344 MHz
XRAE
D3
12 kHz
XA4
D2
CS2 = 0
D1
res
24 kHz
D0
rbc
Alternate Feature Status (I24)
Default = x0000000
PU
PO
CO
CU
PI
CI
The PI and CI bits are reset by writing a "0" to
the particular interrupt bit or by writing any
value to the Status register (R2).
D7
res
D6
rbc
CrystalClear Portable ISA Audio System
D5
CI
Playback Underrun: When set,
indicates the DAC has run out of
data and a sample has been missed.
Playback Overrun: When set,
indicates that the host attempted to
write data into a full FIFO and the
data was discarded.
Capture Overrun: When set,
indicates that the ADC had a sample
to load into the FIFO but the FIFO
was full. In this case, this bit is set
and the new sample is discarded.
Capture Underrun: Indicates the host
has read more data out of the FIFO
than it contained. In this condition,
the bit is set and the last valid byte
is read by the host.
Playback Interrupt: Indicates an
interrupt is pending from the play-
back DMA count registers.
Capture Interrupt: Indicates an
interrupt is pending from the capture
DMA count registers.
D4
TM
PI
D3
CU
D2
CO
D1
PO
CS4239
DS253PP2
D0
PU