cs4215 Cirrus Logic, Inc., cs4215 Datasheet - Page 5

• Manufacturer Part Number: cs4215
• Description: 16-bit Multimedia Audio Codec
• Manufacturer: Cirrus Logic, Inc.

SWITCHING CHARACTERISTICS
outputs loaded with 30 pF; Input Levels: Logic 0 = 0V, Logic 1 = VD1, VD2)
Notes: 8. In Master mode with BSEL1,0 set to 64 or 128 bits per frame (bpf), the SCLK duty cycle is 50%.
DS76F2
SCLK period
SCLK high time
SCLK low time
Input Setup Time
Input Hold Time
Input Transition Time
Output delay
SCLK to TSOUT
Output to Hi-Z state
Output to non-Hi-Z
Input Clock Frequency
Input Clock (CLKIN) low time
Input Clock (CLKIN) high time
Sample rate
RESET low time
FSYNC in
TSIN
TSOUT
FSYNC out
SCLK
SDIN
SDOUT
10. Sample rate specifications must not be exceeded.
11. After powering up the CS4215, RESET should be held low for 50 ms to allow the voltage
9. In Slave mode, FSYNC and SCLK must be derived from the master clock running the codec
When BSEL1,0 is set to 256 bpf, SCLK will have the same duty cycle as CLKOUT.
See Internal Clock Generation section.
(CLKIN, XTAL1, XTAL2).
reference to settle.
t s1
t sckh
t
Parameter
pd1
t h1
Master Mode, XCLK = 1 (Note 8)
Slave Mode, XCLK = 0 (Note 9)
Slave Mode, XCLK = 0 (Note 9)
t s1
t
sckw
Slave Mode (XCLK = 0)
t
t h1
t
pd1
nz
10% to 90% points
CLKIN (Note 10)
Timeslot 8, bit 0
Timeslot 1, bit 7
t sckl
t
t
s1
pd1
(T
TS 1, Bit 7
TS 1, Bit 7
A
(Note 11)
Crystals
= 25 C; VA1, VA2, VD1, VD2 = +5V,
t
h1
Symbol
t sckw
tsckw
tsckh
TS 1, Bit 6
TS 1, Bit 6
tsckl
tpd1
tpd2
t h1
t s1
t hz
t nz
Fs
t pd1
1.024
Min
500
80
25
25
15
10
15
30
30
4
-
-
-
-
-
-
t
1/(Fs * bpf)
pd2
Typ
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
CS4215
TS 8, Bit 0
TS 8, Bit 0
Max
13.5
10
28
30
12
27
50
-
-
-
-
-
-
-
-
-
-
t
Units
t
MHz
MHz
pd2
kHz
hz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
5