s908ey16g2vfar Freescale Semiconductor, Inc, s908ey16g2vfar Datasheet - Page 140

• Manufacturer Part Number: s908ey16g2vfar
• Description: M68hc08 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

Enhanced Serial Communications Interface (ESCI) Module
After a complete character shifts into the receive shift register, the data portion of the character transfers
to the SCDR. The ESCI receiver full bit, SCRF, in ESCI status register 1 (SCS1) becomes set, indicating
that the received byte can be read. If the ESCI receive interrupt enable bit, SCRIE, in SCC2 is also set,
the SCRF bit generates a receiver CPU interrupt request.
13.4.3.3 Data Sampling
The receiver samples the RxD pin at the RT clock rate. The RT clock is an internal signal with a frequency
16 times the baud rate. To adjust for baud rate mismatch, the RT clock is resynchronized at these times
(see
To locate the start bit, data recovery logic does an asynchronous search for a 0 preceded by three 1s.
When the falling edge of a possible start bit occurs, the RT clock begins to count to 16.
To verify the start bit and to detect noise, data recovery logic takes samples at RT3, RT5, and RT7.
Table 13-2
If start bit verification is not successful, the RT clock is reset and a new search for a start bit begins.
140
•
•
Figure
After every start bit
After the receiver detects a data bit change from 1 to 0 (after the majority of data bit samples at
RT8, RT9, and RT10 returns a valid 1 and the majority of the next RT8, RT9, and RT10 samples
returns a valid 0)
summarizes the results of the start bit verification samples.
13-6):
RT CLOCK
RT CLOCK
SAMPLES
CLOCK
RESET
STATE
RxD
RT
RT3, RT5, and RT7 Samples
MC68HC908EY16A • MC68HC908EY8A Data Sheet, Rev. 1
Figure 13-6. Receiver Data Sampling
000
001
010
011
100
101
110
111
QUALIFICATION
Table 13-2. Start Bit Verification
START BIT
VERIFICATION
START BIT
Start Bit Verification
START BIT
Yes
Yes
Yes
Yes
No
No
No
No
SAMPLING
DATA
Noise Flag
0
1
1
0
1
0
0
0
Freescale Semiconductor
LSB