s908ey16g2vfar Freescale Semiconductor, Inc, s908ey16g2vfar Datasheet - Page 65

• Manufacturer Part Number: s908ey16g2vfar
• Description: M68hc08 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

STOP — STOP Instruction Enable Bit
COPD — COP Disable Bit
ESCIBDSRC — ESCI Baud Rate Clock Source Bit
EXTXTALEN — External Crystal Enable Bit
Freescale Semiconductor
If the system clock source selected is the internal oscillator or the external crystal and the
OSCENINSTOP configuration bit is not set, the oscillator will be disabled during stop mode. The short
stop recovery does not provide enough time for oscillator stabilization and thus the SSREC bit should
not be set.
The system stabilization time for power-on reset and long stop recovery (both 4096 CGMXCLK cycles)
gives a delay longer than the LVI enable time for these startup scenarios. There is no period where the
MCU is not protected from a low-power condition. However, when using the short stop recovery
configuration option, the 32-CGMXCLK delay must be greater than the LVI’s turn on time to avoid a
period in startup where the LVI is not protecting the MCU.
STOP enables the STOP instruction.
COPD disables the COP module. See
ESCIBDSRC controls the clock source used for the ESCI. The setting of the bit affects the frequency
at which the ESCI operates.
EXTXTALEN enables the external oscillator circuits to be configured for a crystal configuration where
the PTC4/OSC1 and PTC3/OSC2 pins are the connections for an external crystal.
Clearing the EXTXTALEN bit (default setting) allows the PTC3/OSC2 pin to function as a
general-purpose I/O pin. Refer to
Chapter 8 Internal Clock Generator (ICG) Module
operation.
EXTXTALEN, when set, also configures the clock monitor to expect an external clock source in the
valid range of crystals (30 kHz to 100 kHz or 1 MHz to 8 MHz). When EXTXTALEN is clear, the clock
monitor will expect an external clock source in the valid range for externally generated clocks when
using the clock monitor (60 Hz to 32 MHz).
1 = STOP instruction enabled
0 = STOP instruction treated as illegal opcode
1 = COP module disabled
0 = COP module enabled
1 = Internal data bus clock used as clock source for ESCI
0 = CGMXCLK used as clock source for ESCI
Address:
Reset:
Read:
Write:
This bit does not function without setting the EXTCLKEN bit also.
$001E
Bit 7
R
R
0
ESCIBDSRC EXTXTALEN EXTSLOW EXTCLKEN TMBCLKSEL OSCENINSTOP SSBPUENB
= Reserved
Figure 5-2. Configuration Register 2 (CONFIG2)
MC68HC908EY16A • MC68HC908EY8A Data Sheet, Rev. 1
6
0
Table 5-1
5
0
Chapter 6 Computer Operating
for configuration options for the external source. See
NOTE
4
0
for a more detailed description of the external clock
3
0
2
0
Properly.
1
0
Functional Description
Bit 0
1
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