mt48lc16m16a2 Micron Semiconductor Products, mt48lc16m16a2 Datasheet - Page 48
mt48lc16m16a2
Manufacturer Part Number
mt48lc16m16a2
Description
256mb X4, X8, X16 Sdram
Manufacturer
Micron Semiconductor Products
Datasheet
1.MT48LC16M16A2.pdf
(62 pages)
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DQML, DQMU
TIMING PARAMETERS
NOTE: 1. For this example, the burst length = 1, and the CAS latency = 2.
256Mb: x4, x8, x16 SDRAM
256MSDRAM_E.p65 – Rev. E; Pub. 3/02
*CAS latency indicated in parentheses.
SYMBOL*
t
t
t
t
t
t
t
t
t
t
COMMAND
A0-A9, A11
AC (3)
AC (2)
AH
AS
CH
CL
CK (3)
CK (2)
CKH
CKS
BA0, BA1
DQM /
CKE
CLK
A10
DQ
2. x16: A9, A11, and A12 = “Don’t Care”
3. READ command not allowed else
x8: A11 and A12 = “Don’t Care”
x4: A12 = “Don’t Care”
t CKS
t CMS
t AS
t AS
t AS
MIN
0.8
1.5
2.5
2.5
7.5
0.8
1.5
ACTIVE
7
T0
ROW
ROW
BANK
t CMH
t CKH
t AH
t AH
t AH
-7E
t RCD
t RAS
t RC
MAX
5.4
5.4
t CK
T1
NOP
SINGLE READ – WITH AUTO PRECHARGE
MIN
0.8
1.5
2.5
2.5
7.5
0.8
1.5
10
t CL
-75
T2
NOP 3
t
t CH
RAS would be violated
MAX
5.4
6
T3
UNITS
NOP 3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ENABLE AUTO PRECHARGE
t CMS
48
COLUMN m 2
BANK
T4
READ
t CMH
CAS Latency
SYMBOL*
t
t
t
t
t
t
t
t
t
t
CMH
CMS
HZ (3)
HZ (2)
LZ
OH
RAS
RC
RCD
RP
T5
NOP
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t AC
MIN
t RP
0.8
1.5
37
60
15
15
1
3
-7E
D
T6
120,000
OUT
NOP
MAX
256Mb: x4, x8, x16
t OH
5.4
5.4
m
t HZ
1
ACTIVE
MIN
ROW
BANK
T7
0.8
1.5
ROW
44
66
20
20
1
3
-75
120,000
©2002, Micron Technology, Inc.
MAX
SDRAM
5.4
6
T8
NOP
DON’T CARE
UNDEFINED
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns