mt48lc16m16a2 Micron Semiconductor Products, mt48lc16m16a2 Datasheet - Page 52
mt48lc16m16a2
Manufacturer Part Number
mt48lc16m16a2
Description
256mb X4, X8, X16 Sdram
Manufacturer
Micron Semiconductor Products
Datasheet
1.MT48LC16M16A2.pdf
(62 pages)
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TIMING PARAMETERS
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 4, and the WRITE burst is followed by a “manual” PRECHARGE.
256Mb: x4, x8, x16 SDRAM
256MSDRAM_E.p65 – Rev. E; Pub. 3/02
A0-A9, A11, A12
DQML, DQMU
SYMBOL*
t
t
t
t
t
t
t
t
t
AH
AS
CH
CL
CK (3)
CK (2)
CKH
CKS
CMH
COMMAND
BA0, BA1
DQM/
2. 14ns to 15ns is required between <D
3. x16: A9, A11, and A12 = “Don’t Care”
CKE
A10
CLK
DQ
x8: A11 and A12 = “Don’t Care”
x4: A12 = “Don’t Care”
t CMS
t CKS
t AS
t AS
t AS
MIN
0.8
1.5
2.5
2.5
7.5
0.8
1.5
0.8
ACTIVE
7
T0
ROW
ROW
BANK
t CKH
t CMH
t AH
t AH
t AH
-7E
t RCD
t RAS
t RC
MAX
t CK
T1
NOP
DISABLE AUTO PRECHARGE
MIN
t CMS
0.8
1.5
2.5
2.5
7.5
0.8
1.5
0.8
10
t CL
t DS
WRITE – WITHOUT AUTO PRECHARGE
COLUMN m 3
WRITE
T2
BANK
D
-75
IN
t CMH
t CH
t DH
m
MAX
t DS
IN
D
IN
T3
NOP
m+3> and the PRECHARGE command, regardless of frequency.
m + 1
t DH
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
t DS
D
T4
IN
NOP
m + 2
52
t DH
SYMBOL*
t
t
t
t
t
t
t
t
t DS
CMS
DH
DS
RAS
RC
RCD
RP
WR
D
IN
T5
NOP
m + 3
t DH
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MIN
t
1.5
0.8
1.5
37
60
15
15
14
WR
T6
NOP
2
-7E
120,000
1
MAX
256Mb: x4, x8, x16
PRECHARGE
SINGLE BANK
ALL BANKs
T7
BANK
MIN
1.5
0.8
1.5
44
66
20
20
15
t RP
NOP
T8
-75
DON’T CARE
120,000
©2002, Micron Technology, Inc.
MAX
SDRAM
ACTIVE
ROW
ROW
BANK
T9
UNITS
ns
ns
ns
ns
ns
ns
ns
ns