mt48lc16m16a2tg-7e-it Micron Semiconductor Products, mt48lc16m16a2tg-7e-it Datasheet - Page 14

• Manufacturer Part Number: mt48lc16m16a2tg-7e-it
• Description: 256mb X4, X8, X16 Sdram
• Manufacturer: Micron Semiconductor Products

Table 5:
PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8
256MSDRAM_2.fm - Rev. L 10/07 EN
J7, J3, J2, H3,
H2, H1, G3,
D2, D1, C2,
A8, B9, B8,
C9, C8, D9,
H7, H8, J8,
H9, G2, G1
D8, E9, E1,
C1, B2, B1,
F7, F8, F9
54-Ball
G7, G8
FBGA
E8, F1
G9
A2
E2
F2
F3
54-Ball and 60-Ball FBGA Descriptions
M2, N8, M1,
P1, N2, N1,
A8, C7, D8,
N7, P8, P7,
R8, R1, P2,
F7, F2, D1,
C7, F7, F2,
J8, K7, J7
60-Ball
M8, M7
C2, A1
FBGA
K2
C2
L2
L8
L1
J2
CAS#, RAS#,
DQ0–DQ15
DQ0–DQ3
DQ0–DQ7
BA0, BA1
Symbol
A0–A12
LDQM,
UDQM
DQM,
WE#
CLK
CKE
CS#
NC
(x4) I/O Data input/output: Data bus.
(x8) I/O Data input/output: Data bus.
Input
Input
Input
Input
Input
Input
Input
Type
I/O
–
Description
Clock: CLK is driven by the system clock. All SDRAM input signals are
sampled on the positive edge of CLK. CLK also increments the internal
burst counter and controls the output registers.
Clock enable: CKE activates (HIGH) and deactivates (LOW) the CLK
signal. Deactivating the clock provides PRECHARGE power-down and
SELF REFRESH operation (all banks idle), ACTIVE power-down (row
active in any bank), or CLOCK SUSPEND operation (burst/access in
progress). CKE is synchronous except after the device enters power-
down and self refresh modes, where CKE becomes asynchronous until
after exiting the same mode. The input buffers, including CLK, are
disabled during power-down and self refresh modes, providing low
standby power. CKE may be tied HIGH.
Chip select: CS# enables (registered LOW) and disables (registered
HIGH) the command decoder. All commands are masked when CS# is
registered HIGH, but READ/WRITE bursts already in progress will
continue and DQM operation will retain its DQ mask capability while
CS# is HIGH. CS# provides for external bank selection on systems with
multiple banks. CS# is considered part of the command code.
Command inputs: CAS#, RAS#, and WE# (along with CS#) define the
command being entered.
Input/output mask: DQM is sampled HIGH and is an input mask signal
for write accesses and an output enable signal for read accesses. Input
data is masked during a WRITE cycle. The output buffers are placed in
a High-Z state (two-clock latency) when during a READ cycle. LDQM
corresponds to DQ0–DQ7; UDQM corresponds to DQ8–DQ15. LDQM
and UDQM are considered same state when referenced as DQM.
Bank address input(s): BA0 and BA1 define to which bank the ACTIVE,
READ, WRITE, or PRECHARGE command is being applied. These balls
also provide the op-code during a LOAD MODE REGISTER command.
Address inputs: A0–A12 are sampled during the ACTIVE command
(row-address A0–A12) and READ or WRITE command (column-address
A0–A9, A11 [x4]; A0–A9 [x8]; A0–A8 [x16]; with A10 defining auto
precharge) to select one location out of the memory array in the
respective bank. A10 is sampled during a PRECHARGE command to
determine whether all banks are to be precharged (A10 HIGH) or bank
selected by BA0, BA1 (LOW). The address inputs also provide the op-
code during a LOAD MODE REGISTER command.
Data input/output: Data bus.
No connect: These balls should be left unconnected.
14
Pin/Ball Assignments and Descriptions
Micron Technology, Inc., reserves the right to change products or specifications without notice.
256Mb: x4, x8, x16 SDRAM
©1999 Micron Technology, Inc. All rights reserved.