mt48lc16m16a2tg-7e-it Micron Semiconductor Products, mt48lc16m16a2tg-7e-it Datasheet - Page 37

• Manufacturer Part Number: mt48lc16m16a2tg-7e-it
• Description: 256mb X4, X8, X16 Sdram
• Manufacturer: Micron Semiconductor Products

Figure 26:
Clock Suspend
Figure 27:
PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8
256MSDRAM_2.fm - Rev. L 10/07 EN
Power-Down
Clock Suspend During WRITE Burst
COMMAND
The clock suspend mode occurs when a column access/burst is in progress and CKE is
registered LOW. In the clock suspend mode, the internal clock is deactivated, “freezing”
the synchronous logic.
For each positive clock edge on which CKE is sampled LOW, the next internal positive
clock edge is suspended. Any command or data present on the input pins at the time of a
suspended internal clock edge is ignored; any data present on the DQ pins remains
driven; and burst counters are not incremented, as long as the clock is suspended. (See
examples in Figure 27 and Figure 28 on page 38.)
operation will resume on the subsequent positive clock edge.
COMMAND
CKE
Clock suspend mode is exited by registering CKE HIGH; the internal clock and related
CLK
INTERNAL
ADDRESS
CLOCK
All banks idle
Enter power-down mode.
CLK
CKE
D
IN
t CKS
NOP
T0
NOP
TRANSITIONING DATA
WRITE
BANK,
COL n
T1
D
n
IN
Input buffers gated off
T2
37
(
(
(
(
)
(
)
)
)
)
(
(
(
(
)
(
)
)
)
)
T3
Exit power-down mode.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
NOP
n + 1
T4
D
IN
DON’T CARE
> t CKS
T5
NOP
n + 2
D
NOP
IN
256Mb: x4, x8, x16 SDRAM
DON’T CARE
©1999 Micron Technology, Inc. All rights reserved.
ACTIVE
t RCD
t RAS
t RC
Operations