mt48lc16m16a2tg-7e-it Micron Semiconductor Products, mt48lc16m16a2tg-7e-it Datasheet - Page 33

• Manufacturer Part Number: mt48lc16m16a2tg-7e-it
• Description: 256mb X4, X8, X16 Sdram
• Manufacturer: Micron Semiconductor Products

Figure 19:
Figure 20:
PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8
256MSDRAM_2.fm - Rev. L 10/07 EN
WRITE Command
WRITE Burst
Note:
A9, A11, A12: x16
COMMAND
Data for any WRITE burst may be truncated with a subsequent WRITE command, and
data for a fixed-length WRITE burst may be immediately followed by data for a WRITE
command. The new WRITE command can be issued on any clock following the previous
WRITE command, and the data provided coincident with the new command applies to
the new command. An example is shown in Figure 21 on page 34. Data n + 1 is either the
last of a burst of two or the last desired of a longer burst. The 256Mb SDRAM uses a pipe-
lined architecture and therefore does not require the 2n rule associated with a prefetch
architecture. A WRITE command can be initiated on any clock cycle following a previous
WRITE command. Full-speed random write accesses within a page can be performed to
the same bank, as shown in Figure 22 on page 34, or each subsequent WRITE may be
performed to a different bank.
A0–A9, A11: x4
ADDRESS
A11, A12: x8
BL = 2. DQM is LOW.
A0–A9: x8
A0–A8: x16
BA0, BA1
CLK
DQ
A12: x4
CAS#
RAS#
WE#
A10
CLK
CKE
CS#
WRITE
BANK,
COL n
TRANSITIONING DATA
T0
D
n
IN
HIGH
NOP
n + 1
T1
D
IN
DISABLE AUTO PRECHARGE
ENABLE AUTO PRECHARGE
NOP
33
T2
COLUMN
ADDRESS
ADDRESS
BANK
DON’T CARE
T3
NOP
Micron Technology, Inc., reserves the right to change products or specifications without notice.
256Mb: x4, x8, x16 SDRAM
©1999 Micron Technology, Inc. All rights reserved.
Operations