mt48lc16m16a2tg-7e-it Micron Semiconductor Products, mt48lc16m16a2tg-7e-it Datasheet - Page 54

• Manufacturer Part Number: mt48lc16m16a2tg-7e-it
• Description: 256mb X4, X8, X16 Sdram
• Manufacturer: Micron Semiconductor Products

Notes
PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8
256MSDRAM_2.fm - Rev. L 10/07 EN
10.
11. AC operating and I
12. Other input signals are allowed to transition no more than once every two clocks and
13. I
14. Timing actually specified by
15. Timing actually specified by
16. Timing actually specified by
17. Required clocks are specified by JEDEC functionality and are not dependent on any
18. The I
19. Address transitions average one transition every two clocks.
20. CLK must be toggled a minimum of two times during this period.
21. Based on
1. All voltages referenced to V
2. This parameter is sampled. V
3. I
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to indicate cycle time at which proper
6. An initial pause of 100µs is required after power-up, followed by two AUTO REFRESH
7. AC characteristics assume
8. In addition to meeting the transition rate specification, the clock and CKE must tran-
9. Outputs measured at 1.5V with equivalent load:
biased at 1.4V.
with minimum cycle time and the outputs open.
operation over the full temperature range is ensured; (0°C ≤ T
cial) and (–40°C ≤ T
commands, before proper device operation is ensured. (V
ered up simultaneously. V
REFRESH command wake-ups should be repeated any time the
ment is exceeded.
sit between V
t
a reference to V
High-Z.
ment reference level of 1.5V. If the input transition time is longer than 1ns, then the
timing is measured from V
point. CLK should always be 1.5V referenced to crossover. Refer to Micron technical
note TN-48-09.
are otherwise at valid V
cycle rate.
minimum cycle rate.
timing parameter.
frequency alteration for the test condition.
Q
DD
HZ defines the time at which the output achieves the open circuit condition; it is not
DD
is dependent on output loading and cycle rates. Specified values are obtained
specifications are tested after the device is properly initialized.
DD
current will increase or decrease proportionally according to the amount of
t
CK = 7.5ns for -75 and -7E.
50pF
IH
OH
and V
or V
DD
A
≤ +85°C for IT).
IL
test conditions have V
OL
IH
(or between V
. The last valid data element will meet
SS
or V
IL
t
54
SS
T = 1ns.
and V
t
t
t
(MAX) and V
.
DD
CKS; clock(s) specified as a reference only at minimum
WR plus
WR.
IL
, V
levels.
SS
DD
Q must be at same potential.) The two AUTO
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Q = +3.3V; f = 1 MHz, T
IL
t
RP; clock(s) specified as a reference only at
and V
IH
(MIN) and no longer from the 1.5V mid-
IL
IH
= 0V and V
) in a monotonic manner.
256Mb: x4, x8, x16 SDRAM
IH
DD
= 3.0V using a measure-
©1999 Micron Technology, Inc. All rights reserved.
A
and V
A
= 25°C; pin under test
≤ +70°C for commer-
t
OH before going
t
REF refresh require-
DD
Q must be pow-
Notes