mt45w4mw16bcgb Micron Semiconductor Products, mt45w4mw16bcgb Datasheet - Page 19

• Manufacturer Part Number: mt45w4mw16bcgb
• Description: 64mb 4 Meg X 16 Async/page/burst Cellularram 1.5 Memory
• Manufacturer: Micron Semiconductor Products

Access Using CRE
Figure 12:
PDF: 09005aef8247bd51/Source: 09005aef8247bd83
64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN
(except A[19:18])
A[19:18]
DQ[15:0]
LB#/UB#
A[21:0]
ADV#
WE#
OE#
CRE
CE#
Configuration Register WRITE, Asynchronous Mode Followed by READ ARRAY
1
Notes:
t VPH
The registers can be accessed either using a synchronous or an asynchronous operation
when the control register enable (CRE) input is HIGH (see Figures 12 through 15). When
CRE is LOW, a READ or WRITE operation will access the memory array. The configura-
tion register values are written via addresses A[21:0]. In an asynchronous WRITE, the
values are latched into the configuration register on the rising edge of ADV#, CE#, or
WE#, whichever occurs first; LB# and UB# are “Don’t Care.” The BCR is accessed when
A[19:18] are 10b; the RCR is accessed when A[19:18] are 00b. The DIDR is read when
A[19:18] are 01b. For reads, address inputs other than A[19:18] are “Don’t Care,” and
register bits 15:0 are output on DQ[15:0]. Micron strongly recommends reading the
memory array immediately after performing a configuration register READ and WRITE
operation.
1. A[19:18] = 00b to load RCR and A[19:18] = 10b to load BCR.
Select control register
OPCODE
t AVS
Initiate control register access
64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory
t AVS
t VP
t AVH
t AVH
t CW
Write address bus value
19
to control register
t WP
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t CBPH
Address
Address
©2005 Micron Technology, Inc. All rights reserved.
Valid data
Registers
Don’t Care