mt45w4mw16bcgb Micron Semiconductor Products, mt45w4mw16bcgb Datasheet - Page 8

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mt45w4mw16bcgb

Manufacturer Part Number
mt45w4mw16bcgb
Description
64mb 4 Meg X 16 Async/page/burst Cellularram 1.5 Memory
Manufacturer
Micron Semiconductor Products
Datasheet

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Table 2:
PDF: 09005aef8247bd51/Source: 09005aef8247bd83
64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN
Mode
Read
Write
Standby
No operation
Configuration
register write
Configuration
register read
DPD
Bus Operations – Asynchronous Mode (BCR[15] = 1; Default)
Deep power-down
Notes:
Standby
Power
Active
Active
Active
Active
Idle
1. CLK must be LOW during asynchronous read and asynchronous write modes and to achieve
2. The WAIT polarity is configured through the bus configuration register (BCR[10]).
3. When LB# and UB# are in select mode (LOW), DQ[15:0] are enabled. When only LB# is in
standby power during standby and DPD modes. CLK must be static (HIGH or LOW) during
burst suspend.
select mode, DQ[7:0] are enabled. When only UB# is in the select mode, DQ[15:8] are
enabled.
64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory
CLK
L
L
L
L
L
L
L
1
ADV#
X
X
X
L
L
L
L
CE#
H
H
L
L
L
L
L
8
OE#
X
X
X
H
X
L
L
Micron Technology, Inc., reserves the right to change products or specifications without notice.
WE#
H
H
X
X
X
L
L
CRE
H
H
X
L
L
L
L
LB#/
UB#
X
X
X
X
L
L
L
WAIT
High-Z
High-Z
Low-Z
Low-Z
Low-Z
Low-Z
Low-Z
General Description
©2005 Micron Technology, Inc. All rights reserved.
2
DQ[15:0]
Data-out
reg. out
Data-in
Config.
High-Z
High-Z
High-Z
X
3
Notes
5, 6
4, 6
4
7
4

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