mt45w4mw16bcgb Micron Semiconductor Products, mt45w4mw16bcgb Datasheet - Page 58

• Manufacturer Part Number: mt45w4mw16bcgb
• Description: 64mb 4 Meg X 16 Async/page/burst Cellularram 1.5 Memory
• Manufacturer: Micron Semiconductor Products

Figure 45:
PDF: 09005aef8247bd51/Source: 09005aef8247bd83
64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN
DQ[15:0]
LB#/UB#
A[21:0]
ADV#
WAIT
WE#
OE#
CLK
CE#
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
IH
IH
IL
IH
IL
IH
IL
IL
IH
IL
IH
IL
IH
IL
OH
OL
IH
IL
Burst WRITE at End of Row (Wrap Off)
Notes:
t CLK
Valid input
t SP
1. Nondefault BCR settings for burst WRITE at end of row: fixed or variable latency; WAIT
2. For burst WRITEs, CE# must go HIGH before the third CLK after the WAIT period begins
3. Devices from different CellularRAM vendors can assert WAIT so that the end-of-row data is
4. Micron devices are fully compatible with the CellularRAM Workgroup specification that
active LOW; WAIT asserted during delay.
(before the third CLK after WAIT asserts with BCR[8] = 0 or before the fourth CLK after
WAIT asserts with BCR[8] = 1). Micron devices are fully compatible with the CellularRAM
Workgroup specification that requires CE# to go HIGH 1 cycle sooner than shown here.
input 1 cycle before the WAIT period begins (as shown, solid line) or the same cycle that
asserts WAIT. This difference in behavior will not be noticed by controllers that monitor
WAIT or that use WAIT to abort on an end-of-row condition.
requires CE# to go HIGH 1 cycle sooner than shown here.
t HD
64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory
Valid input
(A[6:0] = 7Fh)
End of row
t HZ
Note 3
t KHTL
Note 2
58
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t HZ
Note 4
©2005 Micron Technology, Inc. All rights reserved.
Timing Diagrams
High-Z
Don’t Care