pi7c8154b Pericom Semiconductor Corporation, pi7c8154b Datasheet - Page 51

• Manufacturer Part Number: pi7c8154b
• Description: Asynchronous 2-port Pci Bridge
• Manufacturer: Pericom Semiconductor Corporation

06-0008
4.3
ORDERING RULES
Table 4-1 shows the ordering relationships of all the transactions and refers by number to the
ordering rules that follow.
Table 4-1 SUMMARY OF TRANSACTION ORDERING
Note: The superscript accompanying some of the table entries refers to any applicable ordering rule
listed in this section. Many entries are not governed by these ordering rules; therefore, the
implementation can choose whether or not the transactions pass each other.
The entries without superscripts reflect the PI7C8154B’s implementation choices.
The following ordering rules describe the transaction relationships. Each ordering rule is followed
by an explanation, and the ordering rules are referred to by number in Table 4-1. These ordering
rules apply to posted write transactions, delayed write and read requests, and delayed write and
read completion transactions crossing PI7C8154B in the same direction. Note that delayed
completion transactions cross PI7C8154B in the direction opposite that of the corresponding
delayed requests.
1. Posted write transactions must complete on the target bus in the order in which they were
received on the initiator bus. The subsequent posted write transaction can be setting a flag that
covers the data in the first posted write transaction; if the second transaction were to complete
before the first transaction, a device checking the flag could subsequently consume stale data.
2. A delayed read request traveling in the same direction as a previously queued posted write
transaction must push the posted write data ahead of it. The posted write transaction must complete
on the target bus before the delayed read request can be attempted on the target bus. The read
transaction can be to the same location as the write data, so if the read transaction were to pass the
write transaction, it would return stale data.
3. A delayed read completion must ‘‘pull’’ ahead of previously queued posted write data traveling
in the same direction. In this case, the read data is traveling in the same direction as the write data,
and the initiator of the read transaction is on the same side of PI7C8154B as the target of the write
transaction. The posted write transaction must complete to the target before the read data is
returned
to the initiator. The read transaction can be a reading to a status register of the initiator of the
posted write data and therefore should not complete until the write transaction is complete.
Pass
Posted Write
Delayed Read Request
Delayed Write Request
Delayed Read Completion
Delayed Write Completion
The acceptance of a posted memory write transaction as a target can never be contingent on the
completion of a non-locked, non-posted transaction as a master. This is true for PI7C8154B
and must also be true for other bus agents. Otherwise, a deadlock can occur.
PI7C8154B accepts posted write transactions, regardless of the state of completion of any
delayed transactions being forwarded across PI7C8154B.
Posted
Write
No
No
No
No
Yes
1
2
4
3
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Delayed Read
Request
Yes
No
No
Yes
Yes
5
Delayed Write
Request
Yes
No
No
Yes
Yes
5
MARCH 2006 REVISION 1.12
Delayed Read
Completion
Yes
Yes
Yes
No
No
ASYNCHRONOUS 2-PORT
5
PCI-to-PCI BRIDGE
Delayed Write
Completion
Yes
Yes
Yes
No
No
PI7C8154B
5