pi7c8154b Pericom Semiconductor Corporation, pi7c8154b Datasheet - Page 52

• Manufacturer Part Number: pi7c8154b
• Description: Asynchronous 2-port Pci Bridge
• Manufacturer: Pericom Semiconductor Corporation

06-0008
4.4
5
5.1
4. Delayed write requests cannot pass previously queued posted write data. For posted memory
write transactions, the delayed write transaction can set a flag that covers the data in the posted
write transaction. If the delayed write request were to complete before the earlier posted write
transaction, a device checking the flag could subsequently consume stale data.
5. Posted write transactions must be given opportunities to pass delayed read and write requests
and completions. Otherwise, deadlocks may occur when some bridges which support delayed
transactions and other bridges which do not support delayed transactions are being used in the same
system. A fairness algorithm is used to arbitrate between the posted write queue and the delayed
transaction queue.
DATA SYNCHRONIZATION
Data synchronization refers to the relationship between interrupt signaling and data delivery. The
PCI Local Bus Specification, Revision 2.2, provides the following alternative methods for
synchronizing data and interrupts:
PI7C8154B does not have a hardware mechanism to guarantee data synchronization for posted
write transactions. Therefore, all posted write transactions must be followed by a read operation,
either from the device to the location just written (or some other location along the same path), or
from the device driver to one of the device registers.
ERROR HANDLING
PI7C8154B checks, forwards, and generates parity on both the primary and secondary interfaces.
To maintain transparency, PI7C8154B always tries to forward the existing parity condition on one
bus to the other bus, along with address and data. PI7C8154B always attempts to be transparent
when reporting errors, but this is not always possible, given the presence of posted data and
delayed transactions.
To support error reporting on the PCI bus, PI7C8154B implements the following:
This chapter provides detailed information about how PI7C8154B handles errors. It also describes
error status reporting and error operation disabling.
ADDRESS PARITY ERRORS
PI7C8154B checks address parity for all transactions on both buses, for all address and all bus
commands. When PI7C8154B detects an address parity error on the primary interface, the
following events occur:
The device signaling the interrupt performs a read of the data just written (software).
The device driver performs a read operation to any register in the interrupting device before
accessing data written by the device (software).
System hardware guarantees that write buffers are flushed before interrupts are forwarded.
PERR# and SERR# signals on both the primary and secondary interfaces
Primary status and secondary status registers
The device-specific P_SERR# event disable register
Page 52 of 111
MARCH 2006 REVISION 1.12
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
PI7C8154B