pi7c8154b Pericom Semiconductor Corporation, pi7c8154b Datasheet - Page 59

• Manufacturer Part Number: pi7c8154b
• Description: Asynchronous 2-port Pci Bridge
• Manufacturer: Pericom Semiconductor Corporation

06-0008
Table 5-4 shows setting the data parity detected bit in the status register of secondary interface.
This bit is set under the following conditions:
Table 5-4 SETTING THE SECONDARY INTERFACE DATA PARITY DETECTED BIT
Note: x=don’t care
Table 5-5 shows assertion of P_PERR#. This signal is set under the following conditions:
Table 5-5 ASSERTION OF P_PERR#
Notes: x=don’t care
Table 5-6 shows assertion of S_PERR# that is set under the following conditions:
0
1
0
0
0
1
0
0
0
1
0
0
1 (de-asserted)
1
0 (asserted)
1
0
1
1
1
0
0
1
1
2
Detected Parity
Detected Bit
The PI7C8154B must be a master on the secondary bus.
The parity error response bit must be set in the bridge control register of secondary interface.
The S_PERR# signal is detected asserted or a parity error is detected on the secondary bus.
Secondary
PI7C8154B is either the target of a write transaction or the initiator of a read transaction on the
primary bus.
The parity-error-response bit must be set in the command register of primary interface.
PI7C8154B detects a data parity error on the primary bus or detects S_PERR# asserted during
the completion phase of a downstream delayed write transaction on the target (secondary) bus.
PI7C8154B is either the target of a write transaction or the initiator of a read transaction on the
secondary bus.
The parity error response bit must be set in the bridge control register of secondary interface.
P_PERR#
2
=The parity error was detected on the target (secondary) bus but not on the initiator (primary) bus.
Transaction Type
Read
Read
Read
Read
Posted Write
Posted Write
Posted Write
Posted Write
Delayed Write
Delayed Write
Delayed Write
Delayed Write
Transaction Type
Read
Read
Read
Read
Posted Write
Posted Write
Posted Write
Posted Write
Delayed Write
Delayed Write
Delayed Write
Delayed Write
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Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Direction
Direction
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Bus Where Error
Bus Where Error
Was Detected
Was Detected
MARCH 2006 REVISION 1.12
ASYNCHRONOUS 2-PORT
Primary / Secondary Parity
Primary/ Secondary Parity
Error Response Bits
Error Response Bits
PCI-to-PCI BRIDGE
x / x
x / 1
x / x
x / x
x / x
x / 1
x / x
x / x
x / x
x / 1
x / x
x / x
x / x
x / x
1 / x
x / x
1 / x
x / x
x / x
x / x
1 / x
1 / 1
x / x
x / x
PI7C8154B