pi7c8154b Pericom Semiconductor Corporation, pi7c8154b Datasheet - Page 54

• Manufacturer Part Number: pi7c8154b
• Description: Asynchronous 2-port Pci Bridge
• Manufacturer: Pericom Semiconductor Corporation

06-0008
5.2.2
5.2.3
READ TRANSACTIONS
When PI7C8154B detects a parity error during a read transaction, the target drives data and data
parity, and the initiator checks parity and conditionally asserts PERR#. For downstream
transactions, when PI7C8154B detects a read data parity error on the secondary bus, the following
events occur:
For upstream transactions, when PI7C8154B detects a read data parity error on the primary bus, the
following events occur:
PI7C8154B returns to the initiator the data and parity that was received from the target. When the
initiator detects a parity error on this read data and is enabled to report it, the initiator asserts
PERR# two cycles after the data transfer occurs. It is assumed that the initiator takes responsibility
for handling a parity error condition; therefore, when PI7C8154B detects PERR# asserted while
returning read data to the initiator, PI7C8154B does not take any further action and completes the
transaction normally.
DELAYED WRITE TRANSACTIONS
When PI7C8154B detects a data parity error during a delayed write transaction, the initiator drives
data and data parity, and the target checks parity and conditionally asserts PERR#.
For delayed write transactions, a parity error can occur at the following times:
When a delayed write transaction is normally queued, the address, command, address parity, data,
byte enable bits, and data parity are all captured and a target retry is returned to the initiator. When
PI7C8154B detects a parity error on the write data for the initial delayed write request transaction,
the following events occur:
PI7C8154B asserts S_PERR# two cycles following the data transfer, if the secondary interface
parity error response bit is set in the bridge control register.
PI7C8154B sets the detected parity error bit in the secondary status register.
PI7C8154B sets the data parity detected bit in the secondary status register, if the secondary
interface parity error response bit is set in the bridge control register.
PI7C8154B forwards the bad parity with the data back to the initiator on the primary bus. If the
data with the bad parity is pre-fetched and is not read by the initiator on the primary bus, the
data is discarded and the data with bad parity is not returned to the initiator.
PI7C8154B completes the transaction normally.
PI7C8154B asserts P_PERR# 2 cycles following the data transfer, if the primary interface
parity error response bit is set in the command register.
PI7C8154B sets the detected parity error bit in the primary status register.
PI7C8154B sets the data parity detected bit in the primary status register, if the primary
interface parity-error-response bit is set in the command register.
PI7C8154B forwards the bad parity with the data back to the initiator on the secondary bus. If
the data with the bad parity is pre-fetched and is not read by the initiator on the secondary bus,
the data is discarded and the data with bad parity is not returned to the initiator.
PI7C8154B completes the transaction normally.
During the original delayed write request transaction
When the initiator repeats the delayed write request transaction
When PI7C8154B completes the delayed write transaction to the target
Page 54 of 111
MARCH 2006 REVISION 1.12
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
PI7C8154B