pi7c8154b Pericom Semiconductor Corporation, pi7c8154b Datasheet - Page 73

• Manufacturer Part Number: pi7c8154b
• Description: Asynchronous 2-port Pci Bridge
• Manufacturer: Pericom Semiconductor Corporation

06-0008
13
13.1
13.2
PME# signals are routed from downstream devices around PCI-to-PCI bridges. PME# signals do
not pass through PCI-to-PCI bridges.
RESET
This chapter describes the primary interface, secondary interface, and chip reset mechanisms.
PRIMARY INTERFACE RESET
PI7C8154B has a reset input, P_RESET#. When P_RESET# is asserted, the following events
occur:
P_RESET# asserting and de-asserting edges can be asynchronous to P_CLK and S_CLKOUT.
PI7C8154B is not accessible during P_RESET#. After P_RESET# is de-asserted, PI7C8154B
remains inaccessible for 16 PCI clocks before the first configuration transaction can be accepted.
SECONDARY INTERFACE RESET
The bridge is responsible for driving the secondary bus reset signals, S_RESET#. Bridge asserts
S_RESET# when any of the following conditions are met:
Signal P_RESET# is asserted. Signal S_RESET# remains asserted as long as P_RESET# is
asserted and does not de-assert until P_RESET# is de-asserted.
The secondary reset bit in the bridge control register is set. Signal S_RESET# remains asserted
until a configuration write operation clears the secondary reset bit.
The chip reset bit in the diagnostic control register is set. S_RESET# remains asserted until a
configuration write operation clears the secondary reset bit. The S_RESET# in asserting and de-
asserting edges can be asynchronous to P_CLK.
D0
D3
D3
D3
Current Status
HOT
COLD
COLD
PI7C8154B immediately tri-states all primary PCI interface signals. S_AD[31:0] and
S_CBE[3:0] are driven LOW on the secondary interface and other control signals are tri-stated.
PI7C8154B performs a chip reset.
Registers that have default values are reset.
PI7C8154B samples P_REQ64# to determine whether the 64-bit extension is enabled on the
primary.
D1
D0
D3
D0
COLD
Next State
Page 73 of 111
Unimplemented. PI7C8154B will ignore the write to the power state bits.
Power state will remain at D0.
PI7C8154B enables secondary clock outputs and performs an internal
chip reset. Signal S_RST# will not be asserted. All registers will be
returned to the reset values and buffers will be cleared.
Power has been removed from PI7C8154B. A power-up reset must be
performed to bring PI7C8154B to D0.
Power-up reset. PI7C8154B performs the standard power-up reset
functions as described in Section 11.
Action
MARCH 2006 REVISION 1.12
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
PI7C8154B