pi7c8154b Pericom Semiconductor Corporation, pi7c8154b Datasheet - Page 65

• Manufacturer Part Number: pi7c8154b
• Description: Asynchronous 2-port Pci Bridge
• Manufacturer: Pericom Semiconductor Corporation

06-0008
The secondary arbiter supports a 2-sets programmable 2-level rotating algorithm with each set
taking care of 4 requests / grants. Each set of masters can be assigned to a high priority group and a
low priority group. The low priority group as a whole represents one entry in the high priority
group; that is, if the high priority group consists of n masters, then in at least every n+1 transactions
the highest priority is assigned to the low priority group. Priority rotates evenly among the low
priority group. Therefore, members of the high priority group can be serviced n transactions out of
n+1, while one member of the low priority group is serviced once every n+1 transactions. Figure
7-1 shows an example of an internal arbiter where four masters, including the bridge, are in the
high priority group, and five masters are in the low priority group. Using this example, if all
requests are always asserted, the highest priority rotates among the masters in the following fashion
(high priority members are given in italics, low priority members, in boldface type): B, m0, m1, m2,
m3, B, m0, m1, m2, m4, B, m0, m1, m2, m5, B, m0, m1, m2, m6 and so on.
Each bus master, including PI7C8154B, can be configured to be in either the low priority group or
the high priority group by setting the corresponding priority bit in the arbiter-control register. The
arbiter-control register is located at offset 40h. Each master has a corresponding bit. If the bit is set
to 1, the master is assigned to the high priority group. If the bit is set to 0, the master is assigned to
the low priority group. If all the masters are assigned to one group, the algorithm defaults to a
straight rotating priority among all the masters. After reset, all external masters are assigned to the
low priority group, and PI7C8154B is assigned to the high priority group. PI7C8154B receives
highest priority on the target bus every other transaction and priority rotates evenly among the
other masters.
Priorities are re-evaluated every time S_FRAME# is asserted at the start of each new transaction on
the secondary PCI bus. From this point until the time that the next transaction starts, the arbiter
asserts the grant signal corresponding to the highest priority request that is asserted. If a grant for a
particular request is asserted, and a higher priority request subsequently asserts, the arbiter de-
asserts the asserted grant signal and asserts the grant corresponding to the new higher priority
request on the next PCI clock cycle. When priorities are re-evaluated, the highest priority is
assigned to the next highest priority master relative to the master that initiated the previous
transaction. The master that initiated the last transaction now has the lowest priority in its group.
If PI7C8154B detects that an initiator has failed to assert S_FRAME# after 16 cycles of both grant
assertion and a secondary idle bus condition, the arbiter de-asserts the grant.
To prevent bus contention, if the secondary PCI bus is idle, the arbiter never asserts one grant
signal in the same PCI cycle in which it de-asserts another. It de-asserts one grant and asserts the
next grant, no earlier than one PCI clock cycle later. If the secondary PCI bus is busy, that is,
m1
m0
m2
Figure 7-1 SECONDARY ARBITER EXAMPLE
B
lpg
Page 65 of 111
m8
m3
m7
m6
m4
m5
MARCH 2006 REVISION 1.12
ASYNCHRONOUS 2-PORT
lpg:
B:
Mx:
PCI-to-PCI BRIDGE
low priority group
PI7C8154B
bus master
PI7C8154B