pi7c8154b Pericom Semiconductor Corporation, pi7c8154b Datasheet - Page 64

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pi7c8154b

Manufacturer Part Number
pi7c8154b
Description
Asynchronous 2-port Pci Bridge
Manufacturer
Pericom Semiconductor Corporation
Datasheet

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06-0008
7
7.1
7.2
7.2.1
When PI7C8154B receives a target abort or a master abort in response to a locked posted write
transaction, PI7C8154B cannot pass back that status to the initiator. PI7C8154B asserts SERR# on
the initiator bus when a target abort or a master abort is received during a locked posted write
transaction, if the SERR# enable bit is set in the command register. Signal SERR# is asserted for
the master abort condition if the master abort mode bit is set in the bridge control register (see
Section 5.4).
PCI BUS ARBITRATION
The bridge must arbitrate for use of the primary bus when forwarding upstream transactions. Also,
it must arbitrate for use of the secondary bus when forwarding downstream transactions. The
arbiter for the primary bus resides external to the bridge, typically on the motherboard. For the
secondary PCI bus, the bridge implements an internal arbiter. This arbiter can be disabled, and an
external arbiter can be used instead. This chapter describes primary and secondary bus arbitration.
PRIMARY PCI BUS ARBITRATION
The bridge implements a request output pin, P_REQ#, and a grant input pin, P_GNT#, for primary
PCI bus arbitration. The bridge asserts P_REQ# when forwarding transactions upstream; that is, it
acts as initiator on the primary PCI bus. As long as at least one pending transaction resides in the
queues in the upstream direction, either posted write data or delayed transaction requests, the
bridge keeps P_REQ# asserted. However, if a target retry, target disconnect, or a target abort is
received in response to a transaction initiated by the bridge on the primary PCI bus, the bridge de-
asserts P_REQ# for two PCI clock cycles.
For all cycles through the bridge, P_REQ# is not asserted until the transaction request has been
completely queued. When P_GNT# is asserted LOW by the primary bus arbiter after the bridge
has asserted P_REQ#, PI7C8154B initiates a transaction on the primary bus during the next PCI
clock cycle. When P_GNT# is asserted to PI7C8154B when P_REQ# is not asserted, the bridge
parks P_AD, P_CBE, and P_PAR by driving them to valid logic levels. When the primary bus is
parked at the bridge and the bridge has a transaction to initiate on the primary bus, the bridge starts
the transaction if P_GNT# was asserted during the previous cycle.
SECONDARY PCI BUS ARBITRATION
The bridge implements an internal secondary PCI bus arbiter. This arbiter supports eight external
masters on the secondary bus in addition to PI7C8154B. The internal arbiter can be disabled, and
an external arbiter can be used instead for secondary bus arbitration.
SECONDARY BUS ARBITRATION USING THE INTERNAL ARBITER
To use the internal arbiter, the secondary bus arbiter enable pin, S_CFN#, must be tied LOW.
PI7C8154B has nine secondary bus request input pins, S_REQ#[8:0], and has nine secondary bus
output grant pins, S_GNT#[8:0], to support external secondary bus masters.
The secondary bus request and grant signals are connected internally to the arbiter and are not
brought out to external pins when S_CFN# is LOW.
Page 64 of 111
MARCH 2006 REVISION 1.12
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
PI7C8154B

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