pi7c8154b Pericom Semiconductor Corporation, pi7c8154b Datasheet - Page 55

• Manufacturer Part Number: pi7c8154b
• Description: Asynchronous 2-port Pci Bridge
• Manufacturer: Pericom Semiconductor Corporation

06-0008
Note: If parity checking is turned off and data parity errors have occurred for queued or subsequent
delayed write transactions on the initiator bus, it is possible that the initiator’s re-attempts of the
write transaction may not match the original queued delayed write information contained in the
delayed transaction queue. In this case, a master timeout condition may occur, possibly resulting in
a system error (P_SERR# assertion).
For downstream transactions, when PI7C8154B is delivering data to the target on the secondary
bus and S_PERR# is asserted by the target, the following events occur:
Similarly, for upstream transactions, when PI7C8154B is delivering data to the target on the
primary bus and P_PERR# is asserted by the target, the following events occur:
A delayed write transaction is completed on the initiator bus when the initiator repeats the write
transaction with the same address, command, data, and byte enable bits as the delayed write
command that is at the head of the posted data queue. Note that the parity bit is not compared when
determining whether the transaction matches those in the delayed transaction queues.
Two cases must be considered:
For downstream delayed write transactions, when the parity error is detected on the initiator bus
and PI7C8154B has write status to return, the following events occur:
If the parity-error-response bit corresponding to the initiator bus is set, PI7C8154B asserts
TRDY# to the initiator and the transaction is not queued. If multiple data phases are requested,
STOP# is also asserted to cause a target disconnect. Two cycles after the data transfer,
PI7C8154B also asserts PERR#.
If the parity-error-response bit is not set, PI7C8154B returns a target retry. It queues the
transaction as usual. PI7C8154B does not assert PERR#. In this case, the initiator repeats the
transaction.
PI7C8154B sets the detected-parity-error bit in the status register corresponding to the initiator
bus, regardless of the state of the parity-error-response bit.
PI7C8154B sets the secondary interface data parity detected bit in the secondary status
register, if the secondary parity error response bit is set in the bridge control register.
PI7C8154B captures the parity error condition to forward it back to the initiator on the primary
bus.
PI7C8154B sets the primary interface data-parity-detected bit in the status register, if the
primary parity-error-response bit is set in the command register.
PI7C8154B captures the parity error condition to forward it back to the initiator on the
secondary bus.
When parity error is detected on the initiator bus on a subsequent re-attempt of the transaction
and was not detected on the target bus.
When parity error is forwarded back from the target bus
PI7C8154B first asserts P_TRDY# and then asserts P_PERR# two cycles later, if the primary
interface parity-error-response bit is set in the command register.
PI7C8154B sets the primary interface parity-error-detected bit in the status register.
Because there was not an exact data and parity match, the write status is not returned and the
transaction remains in the queue.
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MARCH 2006 REVISION 1.12
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
PI7C8154B