pc48f4400p0vt00 Intel Corporation, pc48f4400p0vt00 Datasheet - Page 35

• Manufacturer Part Number: pc48f4400p0vt00
• Description: Intel Strataflash Embedded Memory
• Manufacturer: Intel Corporation

7.3
Table 16.
Datasheet
Asynchronous Specifications
Latching Specifications
Clock Specifications
Synchronous Specifications
R101
R102
R103
R104
R105
R106
R108
R200
R201
R202
R203
R301
R302
R303
R304
Num
R111
R10
R11
R12
R13
R15
R16
R17
R1
R2
R3
R4
R5
R6
R7
R8
R9
t
CHQV
t
Symbol
FCLK/RCLK
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
AVCH/L
VLCH/L
ELCH/L
t
t
t
t
t
t
t
GHQZ
t
CH/CL
GLQV
PHQV
GLQX
EHQZ
GHTZ
VHAX
f
t
AVAV
AVQV
ELQV
ELQX
EHEL
ELTV
EHTZ
GLTV
GLTX
AVVH
ELVH
VLQV
VLVH
VHVL
phvh
t
APA
CLK
CLK
OH
AC Read Specifications
AC Read Specifications for 64/128-Mbit Densities (Sheet 1 of 2)
/ t
CLQV
Read cycle time
Address to output valid
CE# low to output valid
OE# low to output valid
RST# high to output valid
CE# low to output in low-Z
OE# low to output in low-Z
CE# high to output in high-Z
OE# high to output in high-Z
Output hold from first occurring address, CE#, or OE# change
CE# pulse width high
CE# low to WAIT valid
CE# high to WAIT high-Z
OE# low to WAIT valid
OE# low to WAIT in low-Z
OE# high to WAIT in high-Z
Address setup to ADV# high
CE# low to ADV# high
ADV# low to output valid
ADV# pulse width low
ADV# pulse width high
Address hold from ADV# high
Page address access
RST# high to ADV# high
CLK frequency
CLK period
CLK high/low time
CLK fall/rise time
Address setup to CLK
ADV# low setup to CLK
CE# low setup to CLK
CLK to output valid
Intel StrataFlash
Order Number: 306666, Revision: 001
Parameter
®
Embedded Memory (P30)
Min
20
10
10
30
25
85
10
10
0
0
0
0
9
5
9
9
9
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Max
150
85
85
25
24
24
17
20
17
20
85
25
40
20
3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1-Gbit P30 Family
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
April 2005
Notes
1,2,3
1,3,6
1,2
1,3
1,3
1,3
1,3
1,4
1
1
1
1
1
1
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