pc48f4400p0vt00 Intel Corporation, pc48f4400p0vt00 Datasheet - Page 61

• Manufacturer Part Number: pc48f4400p0vt00
• Description: Intel Strataflash Embedded Memory
• Manufacturer: Intel Corporation

11.0
Table 26.
11.1
Datasheet
Programming Operations
The device supports three programming methods: Word Programming (40h/10h), Buffered
Programming (E8h, D0h), and Buffered Enhanced Factory Programming (80h, D0h). See
9.0, “Device Operations” on page 48
the device. The following sections describe device programming in detail.
Successful programming requires the addressed block to be unlocked. If the block is locked down,
WP# must be deasserted and the block must be unlocked before attempting to program the block.
Attempting to program a locked block causes a program error (SR[4] and SR[1] set) and
termination of the operation. See
and unlocking blocks.
The Intel StrataFlash® Embedded Memory (P30) is segmented into multiple Programming
Regions. Programming Regions are made up of 8 or 16 blocks depending on the density. The 64-
and 128-Mbit devices have 8 blocks per Programming Region, while the 256-Mbit has 16 blocks in
each Programming Region (see
address ranges of each Programming Region per density.
Programming Regions per Device
Execute in Place (XIP) is defined as the ability to execute code directly from the flash memory.
XIP applications must partition the memory such that code and data are in separate programming
regions (see
Region should contain only code or data, and not both. The following terms define the difference
between code and data. System designs must use these definitions when partitioning their code and
data for the P30 device.
Word Programming
Word programming operations are initiated by writing the Word Program Setup command to the
device (see
device with the address and data to be programmed. The device outputs Status Register data when
read. See
the specified V
Code :
Data :
Device Density
128-Mbit
256-Mbit
512-Mbit
64-Mbit
1-Gbit
Figure 40, “Word Program Flowchart” on page
Section 9.0, “Device Operations” on page
Execution code ran out of the flash device on a continuous basis in the system.
Information periodically programmed into the flash device and read back (e.g.
execution code shadowed and executed in RAM, pictures, log files, etc.).
Table 26, “Programming Regions per Device” on page
PPL
Intel StrataFlash
min/max values (nominally 1.8 V).
Order Number: 306666, Revision: 001
Number of blocks per
Programming Region
16 blocks
16 blocks
16 blocks
8 blocks
8 blocks
Table
Section 13.0, “Security Modes” on page 69
®
Embedded Memory (P30)
for details on the various programming commands issued to
26). See
Section 4.4, “Memory Maps” on page 24
Number of Programming
Regions per Device
48). This is followed by a second write to the
85. V
16
16
32
64
8
PP
must be above V
61). Each Programming
for details on locking
1-Gbit P30 Family
PPLK
, and within
April 2005
for
Section
61