pc48f4400p0vt00 Intel Corporation, pc48f4400p0vt00 Datasheet - Page 51

• Manufacturer Part Number: pc48f4400p0vt00
• Description: Intel Strataflash Embedded Memory
• Manufacturer: Intel Corporation

Table 20.
9.3
Table 21.
Datasheet
Notes:
1.
2.
3.
4.
Configuration
Protection
Mode
Mode
Read
Write
First command cycle address should be the same as the operation’s target address.
DBA = Device Base Address (NOTE: needed for 2 or more die stacks)
IA = Identification code address offset.
QA = CFI Query address offset.
WA = Word address of memory location to be written.
BA = Address within the block.
PRA = Protection Register address.
LRA = Lock Register address.
RCD = Read Configuration Register data on A[15:0].
ID = Identifier data.
QD = Query data on DQ[15:0].
SRD = Status Register data.
WD = Word data.
N = Word count of data to be loaded into the write buffer.
PD = Protection Register data.
LRD = Lock Register data.
The second cycle of the Buffered Program Command is the word count of the data to be loaded into the write buffer. This
is followed by up to 32 words of data.Then the confirm command (0xD0) is issued, triggering the array programming
operation.
The confirm command (0xD0) is followed by the buffer data.
Program Protection Register
Program Lock Register
Program Read Configuration
Register
Command Bus Cycles (Sheet 2 of 2)
Command Definitions
Valid device command codes and descriptions are shown in
Command Codes and Definitions (Sheet 1 of 2)
Code
0xFF
0x70
0x90
0x98
0x50
0x40
Command
Read Array
Read Status Register
Read Device ID
or Configuration
Register
Read Query
Clear Status Register
Word Program Setup
Device Mode
Intel StrataFlash
Order Number: 306666, Revision: 001
Cycles
Places the device in Read Array mode. Array data is output on DQ[15:0].
Places the device in Read Status Register mode. The device enters this mode
after a program or erase command is issued. Status Register data is output on
DQ[7:0].
Places device in Read Device Identifier mode. Subsequent reads output
manufacturer/device codes, Configuration Register data, Block Lock status, or
Protection Register data on DQ[15:0].
Places the device in Read Query mode. Subsequent reads output Common
Flash Interface information on DQ[7:0].
The WSM can only set Status Register error bits. The Clear Status Register
command is used to clear the SR error bits.
First cycle of a 2-cycle programming command; prepares the CUI for a write
operation. On the next write cycle, the address and data are latched and the
WSM executes the programming algorithm at the addressed location. During
program operations, the device responds only to Read Status Register and
Program Suspend commands. CE# or OE# must be toggled to update the
Status Register in asynchronous read. CE# or ADV# must be toggled to update
the Status Register Data for synchronous Non-array reads. The Read Array
command must be issued to read array data after programming has finished.
Bus
2
2
2
®
Embedded Memory (P30)
Oper
Write
Write
Write
First Bus Cycle
Addr
PRA
RCD
LRA
(1)
Data
Description
0xC0
0xC0
0x60
Table
(2)
21.
Oper
Write
Write
Write
Second Bus Cycle
1-Gbit P30 Family
Addr
RCD
PRA
LRA
(1)
April 2005
Data
0x03
LRD
PD
(2)
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