pc48f4400p0vt00 Intel Corporation, pc48f4400p0vt00 Datasheet - Page 46

• Manufacturer Part Number: pc48f4400p0vt00
• Description: Intel Strataflash Embedded Memory
• Manufacturer: Intel Corporation

1-Gbit P30 Family
8.0
8.1
8.2
April 2005
46
Power and Reset Specifications
Power Up and Down
Power supply sequencing is not required if VCC, VCCQ, and VPP are connected together; If
VCCQ and/or VPP are not connected to the VCC supply, then V
applying V
Power supply transitions should only occur when RST# is low. This protects the device from
accidental programming or erasure during power transitions.
Reset Specifications
Asserting RST# during a system reset is important with automated program/erase devices because
systems typically expect to read from flash memory when coming out of reset. If a CPU reset
occurs without a flash memory reset, proper CPU initialization may not occur. This is because the
flash memory may be providing status information, instead of array data as expected. Connect
RST# to the same active low reset signal used for CPU initialization.
Also, because the device is disabled when RST# is asserted, it ignores its control inputs during
power-up/down. Invalid bus conditions are masked, providing a level of memory protection.
Notes:
1.
2.
3.
4.
5.
6.
7.
Num Symbol
P1 t
P2 t
P3 t
PLPH
PLRH
VCCPH
These specifications are valid for all device versions (packages and speeds).
The device may reset if t
Not applicable if RST# is tied to Vcc.
Sampled, but not 100% tested.
If RST# is tied to the V
If RST# is tied to any supply/signal with V
V
Reset completes within t
CC
CCQ
until V
RST# pulse width low
RST# low to device reset during erase
RST# low to device reset during program
V
and V
CC
Intel StrataFlash
CC
Power valid to RST# de-assertion (high)
Order Number: 306666, Revision: 001
≥ V
PP
CCMIN
. Device inputs should not be driven before supply voltage equals V
CC
.
PLPH
PLPH
supply, device will not be ready until t
Parameter
if RST# is asserted while no erase or program operation is executing.
is < t
®
Embedded Memory (P30)
PLPH
MIN, but this is not guaranteed.
CCQ
voltage levels, the RST# input voltage must not exceed
Min
100
60
-
-
VCCPH
CC
should attain V
after V
Max
25
25
-
-
CC
≥ V
Unit
CCMIN
ns
µs
CCMIN
.
Datasheet
before
1,2,3,4
1,3,4,7
1,3,4,7
1,4,5,6
Notes
CCMIN
.