pc48f4400p0vt00 Intel Corporation, pc48f4400p0vt00 Datasheet - Page 88

• Manufacturer Part Number: pc48f4400p0vt00
• Description: Intel Strataflash Embedded Memory
• Manufacturer: Intel Corporation

1-Gbit P30 Family
Figure 43.
April 2005
88
Standby
Standby
(Note 1)
State
Read
W rite
W rite
W rite
Bus
Operation
Condition
Register
Confirm
Unlock
Status
Done?
Check
BEFP
Setup
BEFP
BEFP
Setup
Block
Error
NOTES:
1. First-word address to be programmed within the target block must be aligned on a write -buffer boundary .
2. Write-buffer contents are programmed sequentially to the flash array starting at the first word address (WSM internally increments addressing ).
BEFP Setup
BEFP Setup delay
Setup Phase
1
1
Check V
BEFP Flowchart
Block Unlocked
errors (SR[3,1])
st
st
V
Data = 0x80 @ 1
Address
Data = 0x80 @ 1
Address
Data = Status Register Data
Address = 1
Check SR[7]:
0 = BEFP Ready
1 = BEFP Not Ready
If SR [7] is set, check:
SR[3] set = V
SR[1] set = Locked Block
Write D0h @
Write 80h @
Status Reg.
V
Word Address
Word Address
PPH
BEFP Setup
PP
Read
Done?
Start
applied to VPP
Exit
BUFFERED ENHANCED FACTORY PROGRAMMING (BEFP) PROCEDURE
applied
PP
No (SR[7]=1)
1
Comments
, Lock
st
PP
Word Addr.
Error
st
st
Yes (SR[7]=0)
W ord
Word
Intel StrataFlash
Order Number: 306666, Revision: 001
Standby
Standby
Standby
Standby
Standby
Standby
(note 2)
No (SR[0]=1)
State
Read
Write
Read
Write
Bus
Program & Verify Phase
Verify Phase
Data Stream
N
Exit Prog &
Operation
Increment
Register
Register
Program
Initialize
Ready?
Done?
Status
Count
Buffer
Count
Buffer
Status
Data?
N
Load
Full?
Last
BEFP Program & Verify
Address Not within
Increment Count:
W rite Data @ 1
Initialize Count:
W ord Address
W rite 0xFFFF,
Current Block
Data Stream
Status Reg.
Status Reg.
®
Program
X = X+1
Ready?
X = 32?
Done?
Check
Data?
Read
X = 0
Read
Last
Embedded Memory (P30)
Data = Status Register Data
Address = 1
Check SR [0]:
0 = Ready for Data
1 = Not Ready for Data
X = 0
Data = Data to Program
Address = 1
X = X+1
X = 32?
Yes = Read SR[0]
No = Load Next Data Word
Data = Status Reg. Data
Address = 1
Check SR [0]:
0 = Program Done
1 = Program in Progress
No = Fill buffer again
Yes = Exit
Data = 0xFFFF @ address
not in current block
Yes (SR[0]=0)
Yes (SR[0]=0)
Y
Y
Comments
st
No (SR[0]=1)
st
st
st
Word Addr.
Word Addr.
Word Addr.
No (SR[7]=0)
Standby
Repeat for subsequent blocks ;
After BEFP exit, a full Status Register check can
determine if any program error occurred ;
See full Status Register check procedure in the
Word Program flowchart.
Write 0xFF to enter Read Array state .
State
Read
Bus
Operation
Register
Full Status Check
Status
Check
Status
Exit Phase
Exit
Status Reg.
Procedure
Complete
Program
Exited?
BEFP
Read
BEFP Exit
Yes (SR[7]=1)
Data = Status Register Data
Address = 1
Check SR[7]:
0 = Exit Not Completed
1 = Exit Completed
Comm ents
st
W ord Addr.
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