mpc9894 ETC-unknow, mpc9894 Datasheet
mpc9894
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mpc9894 Summary of contents
Page 1
... The integrated IDCS continuously monitors all four clock inputs and indicates a clock failure for each clock input. When a false clock signal is detected on the active clock, the MPC9894 switches to a redundant clock input, forcing the PLL to slowly slew to alignment and not produce any phase bumps at the outputs. The MPC9894 also provides a manual mode that allows for user-controlled clock switches ...
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... FB ÷2, ÷4, ÷8, ÷16 IDCS ÷2, ÷4, ÷8, ÷16 Figure 1. MPC9894 Block Diagram Function PLL reference clock inputs (differential) (internal pulldown) PLL feedback signal input (differential). When configured for external feedback, the QFB output should be connected to FB_IN. (internal ...
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... DD V high DD V low DD V high DD V high DD V — — high DD V — DDIC V — DDIC V — DDIC V — DDIC V — DDIC N/A — V — DDA — — — — — — — — — —- — — MPC9894 3 ...
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... CLK_ALARM_RST is a one-shot function Reset of data generators and output dividers. The MPC9894 requires reset at power-up and after any loss of PLL lock. Loss of PLL lock may occur when the external feedback path is interrupted. The length of the reset pulse should be greater than two reference clock ...
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... The MPC9894 will detect and report a missing clock on any of its four inputs. Based upon the current IDCS mode setting and the qualifier input pins, the MPC9894 will switch to the next qualified secondary clock ...
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... I C slave device being accessed. The address for this clock driver is found in the first of the MPC9894 I2C registers. The format of this address has a fixed most-significant four bits of binary 1101 while the least-significant 3 address bits are read from the 3 ADDR pins. This provides the capability to ...
Page 7
... If all four clock inputs are not qualified the VCO will slew to its lowest frequency. This condition will be indicated by the LOCK pin being de-asserted. The MPC9894 will remain in this state until an input clock is restored and the device is reset via the MR pin. ...
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... I C interface prior to operation. If the PRESET pin is high on the release of the MPC9894 powers run state. In this case the IDCS is configured for automatic mode, CLK0 to be the primary clock, a divide clock bank A and B outputs, a divide clock C and D outputs, all clock output banks enabled and interrupts enabled ...
Page 9
... AC parameter tables with the parameter of parameter implies that the output clock edge will never change more than the specified amount in any one cycle. The busy signal is used to indicate that the MPC9894 is in the process of slewing to the new input clock alignment. The signal is accessed thru the clock switch ...
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... M is the PLL feedback divider and output divider. The PLL input divider P, the feedback divider M and the output divider are configured by the device registers 1 and 4. The MPC9894 has four output Table 8. Configuration of PLL P, M and N Frequency Dividers Divider ...
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... C protocol refer to the v2.1 lists the registers that are accessible via the I Register 2 C bus ACK NoACK Data Out Read Stop 2 C interface ADDR_2 ADDR_1 read from read from ADDR[2] pin ADR[1] pin ADDR[0] pin ADDR_0 read from MPC9894 11 ...
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... The mode configuration register, refer to read/write register and contains the fields for mode selection as well as alarm reset. The mode of the MPC9894 may be changed by writing the three least significant Mode Configuration Register bits to the desired value. The current idcs mode of the MPC9894 may be obtained by reading this register ...
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... Advanced Clock Drivers Devices Freescale Semiconductor PLL feedback output QFB cannot be disabled when MPC9894 is configured for external feedback. The Device Configuration Register, bit 6, QUAL_EN is used to enable or disable all clock input qualifier pins. Asserting this bit enables the Clock Qualifier Input Pins CLK_VALID[3:0] ...
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... CLK_STAT[3:0], a clearing of the LOCK bit and a change in the value of the SEL_STAT[1:0] bits. Table 24. Status Register (Register 5 — Read Only) Bit 7 6 Description INT CLK_STAT[3:0] Inverse of Status of CLK3, CLK2, CLK1 and CLK0 (sticky) INT signal Copy of CLK_STAT[3:0] signal MPC9894 Reserved Reserved n/a n/a 0 n/a n/a 0 frequency ranges may overlap allowing a choice of PLL closed loop bandwidths ...
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... Output Power-Down 1 Output Power-Up Feedback Power-Up Register The Feedback Power-Up register bit 0 is used to configure the MPC9894 feedback output in either a power-up state or a power-down state. Note this register bit is valid for internal Table 27. Feedback Power-Up Register (Register 7 — Read/Write) Bit 7 Description ...
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... This section describes the IEEE Std. 1149.1 compliant Test Access Port (TAP) and Boundary Scan Architecture implementation in the MPC9894. Special private instructions are provided to assist in production test control. These instructions combined with control of the test mode inputs Table 29. TAP Interface Signals ...
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... The MPC9894 operates from either a 3 2.5 V voltage supply for the device core. The pin SEL_2P5V is used to logically indicate the core supply voltage. This selection is done by setting the pin to a logic 1 for 2 logic 0 for 3.3 V operation. The input and output supply voltage may be set for either 3 ...
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... Application Note AN1545 for more information). The device AC and DC parameters are specified up to 110°C junction temperature allowing the MPC9894 to be used in applications requiring industrial temperature range recommended that users of the MPC9894 employ thermal modeling analysis to assist in applying the junction temperature specifications to their particular application ...
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... V V DDAB,CD –0.7 Termination 50 Ω DDAB,CD –1.5 –1.4 Ω See Figure 7 Ω See Figure 8 Max Unit Condition V + 0.3 V LVCMOS DD 0.8 V LVCMOS – 0 0.3 V LVCMOS DD 0.7 V LVCMOS – 0 (DC) CMR MPC9894 19 ...
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... PER/CYC Rate of change of period ∆ (11) PER/CYC Rate of change of period Jitter and bandwidth specifications t Cycle-to-cycle jitter JIT(CC) t Period Jitter JIT(PER) t I/O Phase Jitter JIT(∅) BW PLL closed loop bandwidth MPC9894 20 (1) (2) Min Typ = 2.5 V ±5% DDAB,CD,IC 21.25 28.33 56.66 42.5 85.0 113.32 170 (3) 340 ÷2 output 170.0 ÷4 output 85.0 ÷ ...
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... AC characteristics are design targets and pending characterization characteristics apply for parallel output termination of 50 Ω bypass mode, the MPC9894 divides the input reference clock. 4. The input reference frequency must match the VCO lock range divided by the total feedback divider ratio ...
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... MPC9894 Pin and Package Table 40. MPC9894 Pin Listing Signal Name Description CLK0 Clock0 Positive Input CLK0 Clock0 Negative Input CLK1 Clock1 Positive Input CLK1 Clock1 Negative Input CLK2 Clock2 Positive Input CLK2 Clock2 Negative Input CLK3 Clock3 Positive Input CLK3 Clock3 Negative Input ...
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... Table 40. MPC9894 Pin Listing (Continued) Signal Name Description LOCK PLL Lock Indicator CLK_STAT3 Input CLK3 status indicator CLK_STAT2 Input CLK2 status indicator CLK_STAT1 Input CLK1 status indicator CLK_STAT0 Input CLK0 status indicator SEL_STAT1 Reference Clock Selection Indicator (MSB) SEL_STAT0 Reference Clock Selection Indicator (LSB) ...
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... Table 41. MPC9894 Pin Diagram GND QFB DDC V B GND QFB DDIC V C FB_IN FB_IN DD D CLK0 CLK0 TMS V E CLK1 CLK1 DDA F GND CLK2 CLK2 G CLK3 CLK3 TCK H TDI TRST VDDIC V J GND TDO DDAB GND DDIC DDAB ...
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... Description PWR_QD1 PWR_QD0 Reset Default 0 Preset Default 1 Table 49. Feedback Power-Up Register (Register 7 — Read/Write) Bit 7 Description Reset Default Preset Default Advanced Clock Drivers Devices Freescale Semiconductor MPC9894 PROGRAMMING MODEL 5 4 ADD_R5 ADDR_4 ADDR_3 x (TBD) x (TBD) x (TBD) x (TBD) x (TBD) x (TBD FSEL_B[1:0] ...
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... A1 INDEX AREA TOP VIEW INDEX AREA BOTTOM VIEW MPC9894 26 PACKAGE DIMENSIONS 0.2 4X SIDE VIEW (1.18 1.7 MAX 0.43 0.29 0.5 0.55 3 100X 0. CASE 1462-01 ISSUE O NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS. ...
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... Advanced Clock Drivers Devices Freescale Semiconductor NOTES MPC9894 27 ...
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... Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 1-800-441-2447 or 303-675-2140 Fax: 303-675-2150 LDCForFreescaleSemiconductor@hibbertgroup.com MPC9894 Rev. 3 1/2005 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document ...