mpc9894 ETC-unknow, mpc9894 Datasheet - Page 9

• Manufacturer Part Number: mpc9894
• Description: Quad Input Redundant Idcs Clock Generator
• Manufacturer: ETC-unknow

Advanced Clock Drivers Devices
Freescale Semiconductor
automatic mode, follows the next positive edge of the newly
selected reference clock signal. The positive edge of the
feedback clock and the newly selected reference clock edge
will start to slew to alignment by adjusting the feedback edge
placement a small amount of time in each clock cycle.
Figure 2. Clock Switch
the MPC9894 switching to and aligning to the secondary
clock. This small amount of additional time in each clock
cycle will ensure that the output clock does not have any
large phase changes or frequency changes in a short period
of time. The alignment will be to either 1) the closest edge,
secondary clock are 180 degrees out of phase then the
minimum clock transition time can be calculated by
Therefore 180 degree clock difference is
Assuming a
for the alignment to the new clock. The alignment to the new
clock phase may occur slower than this but never faster.
1) the closest edge, either forward or backward or 2) toward
the lagging clock edge. The selection of the alignment
method is selected in the Slew_Control bit (bit 5) of the
Device Configuration and Output Enable Register. This
selection allows the user to select the alignment method that
best suits the application. The characteristics and
subsequent advantages and disadvantages of each method
are described as follows.
1.
An MPC9894 clock switch, either in IDCS manual or IDCS
For example, if the current input clock of 62.5 MHz and the
This is the minimum number of cycles that will be required
The alignment on clock failure is selectable between either
Slew to closest edge
a.
The alignment is either forward toward the lagging
edge or backward toward the leading edge.
t
cycle
∆
PER/CYC
8ns
= 1
÷
÷
40 ps/cycle = 200 cycles.
f
cycle
of 40 ps, then
t
shows a failed primary input clock with
cycle
= 1
Secondary Clock
÷
2 = 8 ns
Primary Clock
÷
Output Clock
62.5 MHz = 16 ns
BUSY
BUSY
CLOCK OUTPUT TRANSITION
Figure 2. Clock Switch
either forward or backward or 2) toward the lagging clock
edge. The maximum rate of period change is specified in the
AC parameter tables with the parameter of
parameter implies that the output clock edge will never
change more than the specified amount in any one cycle.
the process of slewing to the new input clock alignment. The
signal is accessed thru the
clock switch. The pin is reset once the phase realignment is
completed. During the period that
configuration register of the MPC9894 should not be written
with new configuration data.
2.
configuration desired then the reconfiguration of the slew
method should be perform soon after power-up and the
configuration should remain fixed from that point.
The busy signal is used to indicate that the MPC9894 is in
If default values for the Slew_Control is not the
b.
c.
d.
Slew to lagging edge
a.
b.
The alignment to the closest edge ensures
re-alignment to the new clock input in the minimum
time.
In applications where the input clocks are closely
aligned, there is no ambiguity on the direction of
clock slew.
The clock output frequency will either increase or
decrease based on direction of clock slew.
The output frequency always decreases. Thus the
clock frequency never violates a maximum
frequency specification in the user system.
When input clocks are closely aligned (within SPO
+ jitter) the MPC9894 may align to the closest edge
or to the lagging edge. In the case of multiple
MPC9894s with equivalent clock inputs one
MPC9894 may align in one direction while an other
MPC9894 may align to the opposite direction.
BUSY
pin and goes set upon a
BUSY
is active, the
∆
PER/CYC
MPC9894
. This
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