mpc9894 ETC-unknow, mpc9894 Datasheet - Page 8

• Manufacturer Part Number: mpc9894
• Description: Quad Input Redundant Idcs Clock Generator
• Manufacturer: ETC-unknow

IDCS Manual Mode
IDCS_MODE[2:0] = 0xx. The PLL functions normally and all
four inputs clocks are monitored. The reference clock will
always be the clock signal selected by IDCS_MODE[1:0] and
will be indicated by SEL_STAT[1:0]. A manual-requested
clock switch (by changing the IDCS_MODE[0xx] signal) will
only be executed if the new clock is valid. The SEL_STAT[1:0]
pins/bits should be checked after the manual request to
ensure the clock switch occurred.
Interrupt Operation
microprocessor or microcontroller. This open drain output pin
goes active or low on any of the following occurrences
1.
2.
to read the status register (bit 7) to determine if this MPC9894
generated the interrupt. If the interrupt was caused by this
MC9894, the status register would then be analyzed to
determine the reason for the interrupt and then the
appropriate action taken.
the Device Configuration and Output Clock Enable Register.
Once the interrupt flag has been set, reading of the Status
Register clears the INT flag.
Clock Operation on Power-Up
MR
configurations. These configurations are selected by the
PRESET pin and MBOOT pin.
powers up in a benign mode with all clock outputs disabled.
The device is ready to be and must be programmed via the
I
MPC9894 powers up in a run state. In this case the IDCS is
configured for automatic mode, CLK0 to be the primary clock,
a divide by 2 on clock bank A and B outputs, a divide by 8 on
clock C and D outputs, all clock output banks enabled and
interrupts enabled. If using the preset mode, then at least one
of the clock inputs must have the correct input frequency prior
to
MPC9894
8
2
C interface prior to operation.
MR
The manual request IDCS mode is selected by
The MPC9894 pin, INT , may be used to interrupt a
The interrupted processor would then use the I
In order for interrupts to occur, the INT_E bit must be set in
On or after power-up, the MPC9894 must be reset via the
If PRESET is low, on release of the
If the PRESET pin is high on the release of the
pin. The MPC9894 may be powered-up in either of three
A clock failure as indicated by any of bits 6 thru 3 being
set in the status register
A out-of-lock condition for the PLL as indicated by either
the
going high.
LOCK
pin or bit 2 of the status register.
MR
pin, the MPC9894
2
MR
C interface
pin, the
registers describe both configurations. The default (reset)
information is for the normal reset operation, while the default
(preset) information describes the values for each
configuration bit on activation of the PRESET pin. In order to
return the MPC9894 to either the preset or reset configuration
the
pin.
PLL Feedback
an external PLL feedback path. The selection of internal vs.
external feedback is made with the pin, EX_FB_SEL. If
external feedback is desired, the EX_FB_SEL pin should be
connected to V
FB_IN
relationship between the clock input and the feedback input
for phase synchronization of output clock signals to the clock
input. If this phase synchronization is not required, the
MPC9894 may be configured for internal feedback by the
connection of EX_FB_SEL to ground. In this configuration,
the connection from the feedback output to the feedback
input is not required. The feedback output may be used as a
separate output to produce a reference clock output.
PLL Out-of-Lock Conditions
state of the PLL. After power-up and prior to writing
configuration data to the control registers, an out-of-lock
condition will be indicated by
available and proper configuration data is written to the
control registers,
locked condition with
indicate a catastrophic failure of the PLL. This condition will
occur on the following:
1.
2.
repairing the cause of the failure, followed by a master reset
to be issued to the MPC9894.
Later in this document, tables defining the I
Refer to the
The MPC9894 may be operated with either an internal or
The
The combination of
Recovery from the catastrophic failure condition requires
MR
All input clocks have failed or no clock is present.
External feedback has been selected with the
EX_FB_SEL pin and an external feedback signal is not
present on the FB_IN/
that if this condition occurs during the initial PLL lock
acquisition the PLL will produce a clock that is locked to
the internal feedback path. However, the catastrophic
failure status of
must be made. External feedback provides a known
LOCK
pin must be activated.
pin and associated status bit indicates the lock
DD
Boot Mode
LOCK
and a connection from QFB/
LOCK
LOCK
LOCK
will then indicate the PLL is in a
FB_IN
for a description of the MBOOT
= 1 and
Advanced Clock Drivers Devices
= 0.
= 1 and
LOCK
inputs. It should be noted
Freescale Semiconductor
BUSY
= 1. If a valid clock is
BUSY
= 0 will occur.
= 0 is used to
2
QFB
C interface
to FB_IN/