mpc9894 ETC-unknow, mpc9894 Datasheet - Page 11

• Manufacturer Part Number: mpc9894
• Description: Quad Input Redundant Idcs Clock Generator
• Manufacturer: ETC-unknow

Advanced Clock Drivers Devices
Freescale Semiconductor
the registers accessible via the I
values are read or written over the I
Master. This sequence starts with the I
followed by the I
is then followed by the address of the register that is to be
accessed. In the case of a write, the register address byte is
followed by the data to be written to that register. In the case
Boot Mode
via the MBOOT pin, the entire set of writable configuration
registers are written with a 6-byte sequence. This sequence
starts with the Output Configuration Register, and is followed
by the Mode Configuration and Alarm Reset Register, the
Device Configuration and Output Clock Enable Register, the
Input and Feedback Divider Configuration Register, the
Output Power-Up Register and the Feedback Power-Up
Register. This equates to the register sequence of 1, 2, 3, 4,
Slave Address Register
is used to determine if the data on the I
addressed to this device. The seven-bit address is
determined with the fixed value of binary 1101 followed by
Table 10. I
Table 11. Slave Address (Register 0 — Read Only)
Description
Reset default
Preset default
The following tables summarize the bit configurations for
When the I
The Slave Address register contains the I
Bit
2
C Registers
2
Address
C boot mode is activated on power-up or reset
2
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
C device address and read/write byte. This
not used
7
I
2
C INTERFACE AND CONFIGURATION/STATUS REGISTERS
Start
Dev Selection
2
ADDR_6
C interface. The register
2
6
1
1
C interface by the I
Table 11. Slave Address (Register 0 — Read Only)
Table 12. Output Configuration Register (Register 1 — Read/Write)
Table 14. Mode Configuration and Alarm Reset Register (Register 2 — Read/Write)
Table 17. Device Configuration and Output Clock Enable Register (Register 3 — Read/Write)
Table 22. Input and Feedback Divider Configuration Register (Register 4 — Read/Write)
Table 24. Status Register (Register 5 — Read Only)
Table 25. Output Power-Up Register (Register 6 — Read/Write)
Table 27. Feedback Power-Up Register (Register 7 — Read/Write)
2
2
C start command,
C interface is
Figure 4. Boot Mode Random Access Read
2
C address that
Write
ADD_R5
ACK
5
1
1
Byte Addr
2
C
ADDR_4
Start
ACK
4
0
0
Dev Selection
of a read, the device will then respond with the data from that
register. At the conclusion of the transfer an I
command is issued by the Master to terminate the transfer.
For a complete description of the I
I
interface.
6, 7. This sequence starts with the start command, the device
select and read/write(write) byte, followed by the beginning
byte address for reading from the EEPROM. This is then
followed by the start command, device select and read/write
(read) and four current address read bytes. The device
address is the binary 7-bit value of 1010000. This I
sequence is compatible with industry standard I
EEPROMs such as STMicroelectronics M24C01, or
equivalent.
variable bits that are obtained from the three address pins.
The three input pins allow for 8 different addresses for a given
clock generator, allowing up to 8 clock generators to be
addressed on a single I
2
C specification.
Table 10
ADDR_3
3
1
1
Register
Read
lists the registers that are accessible via the I
ACK
Data Out
ADDR[2] pin
read from
ADDR_2
2
C interface.
2
Stop
NoACK
2
C protocol refer to the v2.1
ADR[1] pin
read from
ADDR_1
1
2
C Stop
2
ADDR[0] pin
C bus
read from
ADDR_0
MPC9894
2
C
0
2
11
C