mpc9894 ETC-unknow, mpc9894 Datasheet - Page 10

• Manufacturer Part Number: mpc9894
• Description: Quad Input Redundant Idcs Clock Generator
• Manufacturer: ETC-unknow

requires programming the internal PLL input, feedback and
output dividers. The output frequency is represented by the
following formula:
where f
clock source (reference input), M is the PLL feedback divider
and N is an output divider. The PLL input divider P, the
feedback divider M and the output divider are configured by
the device registers 1 and 4. The MPC9894 has four output
input divider (P) and feedback-divider (M) is limited by the
specified VCO frequency range. f
configured to match the VCO frequency range of 340 to
680 MHz in order to achieve stable PLL operation:
in the specified frequency range. The PLL input divider
effectively extends the usable input frequency range.
MPC9894
10
Table 8. Configuration of PLL P, M and N Frequency Dividers
PLL Input Divider (P)
PLL Feedback Divider (M)
PLL Output Divider, Bank A (N
PLL Output Divider, Bank B (N
PLL Output Divider, Bank C (N
PLL Output Divider, Bank D (N
Table 9. Input and Output Frequency Ranges
Input_FB_Div[3:0]
Configuring the MPC9894 input and output frequencies
The reference frequency f
The PLL input divider (P) can be used to situate the VCO
REF
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
is the reference frequency of the selected input
f
VCO,MIN
f
Divider
OUT
≤
= [(f
(f
÷1
÷1
÷2
÷1
÷2
÷2
÷3
÷4
÷4
P
4
6
REF
REF
A
B
C
D
REF
÷
)
)
)
)
÷
P
÷16
÷12
÷12
÷16
÷12
÷16
÷12
÷12
INPUT AND OUTPUT FREQUENCY CONFIGURATION
÷8
÷8
÷8
and the selection of the PLL
P)
M
⋅
REF
M)
⋅
M]
, P and M must be
≤
f
113.32 – 226.64
÷
VCO,MAX
56.66 – 113.34
28.33 – 56.67
170.0 – 340.0
170.0 – 340.0
21.25 – 42.5
85.0 – 170.0
85.0 – 170.0
85.0 – 170.0
f
42.5 – 85.0
42.5 – 85.0
N
REF
÷1, ÷2, ÷3, ÷4, ÷6
÷8, ÷12, ÷16
÷2, ÷4, ÷8, ÷16
÷2, ÷4, ÷8, ÷16
÷2, ÷4, ÷8, ÷16
÷2, ÷4, ÷8, ÷16
MHz
range
Available Values
Output frequency for any bank A, B, C or D (FSEL_x) and ratio to f
1.5⋅f
8⋅f
6⋅f
3⋅f
4⋅f
4⋅f
2⋅f
2⋅f
2⋅f
1⋅f
1⋅f
N = 2
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
banks (Bank A, B, C, and D) and each output bank can be
configured individually as shown in
the VCO frequency and output divider (N):
configurations of the MPC9894. Note that the VCO lock
range is always 340 MHz to 680 MHz, setting lower and
upper boundaries for the frequency range of the device.
The output frequency for each bank can be derived from
Table 9
reserved
reserved
reserved
reserved
reserved
f
REF
illustrates the possible input clock frequency
0.75⋅f
Figure 3. PLL Frequency Calculation
1.5⋅f
0.5⋅f
0.5⋅f
4⋅f
3⋅f
2⋅f
2⋅f
1⋅f
1⋅f
1⋅f
N = 4
÷P
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
Input_FB_Div[3:0], Register 4, bit 3:0
FSEL_B[1:0], Register 1, bit 7:6
FSEL_B[1:0], Register 1, bit 5:4
FSEL_C[1:0], Register 1, bit 3:2
FSEL_D[1:0], Register 1, bit 1:0
f
f
f
f
QC
QD
QA
QB
[1:0] = f
[1:0] = f
[1:0] = f
[1:0] = f
÷M
PLL
Advanced Clock Drivers Devices
Configuration Through
0.375⋅f
0.75⋅f
0.25⋅f
0.25⋅f
1.5⋅f
0.5⋅f
0.5⋅f
0.5⋅f
2⋅f
1⋅f
1⋅f
N = 8
VCO
VCO
VCO
VCO
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
Freescale Semiconductor
Table
÷
÷
÷
÷
N
N
N
N
A
B
C
D
÷N
8.
0.1875⋅f
0.375⋅f
0.125⋅f
0.125⋅f
0.125⋅f
0.125⋅f
0.125⋅f
0.75⋅f
0.5⋅f
0.5⋅f
N = 16
f
f
REF
OUT
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF