mpc9894 ETC-unknow, mpc9894 Datasheet - Page 20

• Manufacturer Part Number: mpc9894
• Description: Quad Input Redundant Idcs Clock Generator
• Manufacturer: ETC-unknow

MPC9894
20
Table 39. AC Characteristics (T
V
Input and output timing specification
f
f
f
f
f
mae
t
DC
f
Differential input and output voltages
V
V
V
V
PLL and IDCS specifications
t
t
∆
∆
Jitter and bandwidth specifications
t
t
t
BW
REF
VCO
MAX
REFDC
REFacc
r
I2C
(∅)
sk(O)
JIT(CC)
JIT(PER)
JIT(∅)
PER/CYC
PER/CYC
, t
DD
PP
PP, OK
PP, NOK
O(P-P)
f
Symbol
(∅)
= 3.3 V ±5%, V
Input reference frequency
Input reference frequency in PLL bypass mode
VCO frequency range
Output Frequency
Reference Input Duty Cycle
Input Frequency Accuracy
Misaligned Edge Specification
Output Rise/Fall Time
Output duty cycle
I
Differential input voltage
Differential input voltage
Differential input voltage
Differential output voltage (peak-to-peak) (PECL)
Propagation Delay (static phase offset)
CLKX,
Output-to-output Skew within a bank
Output-to-output Skew across a bank
Rate of change of period
Rate of change of period
Cycle-to-cycle jitter
Period Jitter
I/O Phase Jitter
PLL closed loop bandwidth
2
C frequency range
DDAB,CD,IC
CLKX
to FB_IN,
= 3.3 V ±5% or V
Characteristics
J
(4)
= –40°C to +110°C)
FB_IN
(6)
(7)
(8)
(10)
(11)
(5)
(peak-to-peak) (PECL)
(peak-to-peak) (PECL)
(peak-to-peak) (PECL)
(12)
DDAB,CD,IC
(9)
(9)
÷16 output
RMS (1 σ)
RMS (1 σ)
RMS (1 σ)
÷16 output
÷16 output
÷2 output
÷4 output
÷2 output
÷8 output
÷4 output
÷8 output
÷8 output
÷2 output
÷4 output
= 2.5 V ±5%
(1) (2)
(3)
113.32
21.25
28.33
56.66
170.0
21.25
±
–100
42.5
85.0
85.0
42.5
47.5
Min
170
340
0.3
0.3
40
600
Typ
0.8
50
2
113.34
226.68
±
56.67
340.0
170.0
5000
+120
+160
±
±
Max
42.5
85.0
42.5
52.5
+40
+80
±
±
170
340
340
680
1600
800
400
150
100
1.3
0.1
85
60
50
10
15
10
15
30
120
160
40
80
Advanced Clock Drivers Devices
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ppm
MHz
kHz
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
%
%
V
V
V
V
Freescale Semiconductor
Input_FB_Div[3:0] = 0
Input_FB_Div[3:0] = 1
Input_FB_Div[3:0] = 2
Input_FB_Div[3:0] = 3,4
Input_FB_Div[3:0] = 6,7,8
Input_FB_Div[3:0] = 10
Input_FB_Div[3:0] = 14,15
PLL bypass
20% to 80%
PLL locked with external
feedback selected
slew_control = 1
slew_control = 0
N = 2, 2, 2, 2
N = 4, 4, 4, 4
N = 8, 8, 8, 8
N = 16, 16, 16, 16
N = 2, 2, 2, 2
N = 4, 4, 4, 4
N = 8, 8, 8, 8
N = 16, 16, 16, 16
PLL locked
Condition