mpc9894 ETC-unknow, mpc9894 Datasheet - Page 2

• Manufacturer Part Number: mpc9894
• Description: Quad Input Redundant Idcs Clock Generator
• Manufacturer: ETC-unknow

MPC9894
2
Table 1. Pin Configurations
Clock Inputs and Outputs
CLK0, CLK0
CLK1, CLK1
CLK2, CLK2
CLK3, CLK3
FB_IN, FB_IN
QA[1:0], QA[1:0]
QB[1:0], QB[1:0]
QC[1:0], QC[1:0]
QD[1:0], QD[1:0]
QFB, QFB
CLK_ALARM_RST
CLK_VALID[3:0]
MSTROUT_EN
PLL_BYPASS
PLL_TST[2:0]
EX_FB_SEL
ADDR[0:2]
Pin
JTAG[4:0]
PRESET
MBOOT
MEDIA
FB_IN
FB_IN
CLK0
CLK0
CLK1
CLK1
CLK2
CLK2
CLK3
CLK3
SDA
SCL
TPA
MR
Output
Output
Output
Output
Output
Input
Input
I/O
00
01
10
11
Control Logic
I
2
C Interface
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
Type
÷P
÷P
PLL reference clock inputs (differential)
(internal pulldown)
PLL feedback signal input (differential). When configured for external
feedback, the QFB output should be connected to FB_IN. (internal
pulldown)
Bank A differential outputs
Bank B differential outputs
Bank C differential outputs
Bank D differential outputs
Differential PLL feedback output. QFB must be connected to FB_IN for
correct operation
f
comp
Comp
FB
340 – 680 MHz
Figure 1. MPC9894 Block Diagram
IDCS
PLL
DEVICE DESCRIPTION
1
0
Function
÷2, ÷4, ÷8, ÷16
÷2, ÷4, ÷8, ÷16
÷2, ÷4, ÷8, ÷16
÷2, ÷4, ÷8, ÷16
÷M/P
Advanced Clock Drivers Devices
Freescale Semiconductor
Supply
V
V
V
V
V
V
V
DDCD
DDCD
DDCD
DDAB
DDAB
DDIC
DDIC
QB0
QC0
QD1
QA0
QA0
QA1
QA1
QB0
QB1
QB1
QC0
QC1
QC1
QD0
QD0
QD1
QFB
QFB
LOCK
BUSY
INT
SEL_STAT[1:0]
CLK_STAT[3:0]
Active State
—
—
—
—
—
—
—