mpc9894 ETC-unknow, mpc9894 Datasheet - Page 22

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mpc9894

Manufacturer Part Number
mpc9894
Description
Quad Input Redundant Idcs Clock Generator
Manufacturer
ETC-unknow
Datasheet

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MPC9894 Pin and Package
MPC9894
22
Table 40. MPC9894 Pin Listing
CLK_ALARM_RST Reset of all four alarm status flags and clock
PLL_BYPASS
Signal Name
CLK_VALID3
CLK_VALID2
CLK_VALID1
CLK_VALID0
ADDR2
ADDR1
ADDR0
MEDIA
FB_IN
FB_IN
CLK0
CLK0
CLK1
CLK1
CLK2
CLK2
CLK3
CLK3
QA0
QA0
QA1
QA1
QB0
QB0
QB1
QB1
QC0
QC0
QC1
QC1
QD0
QD0
QD1
QD1
QFB
QFB
SCL
SDA
MR
Clock0 Positive Input
Clock0 Negative Input
Clock1 Positive Input
Clock1 Negative Input
Clock2 Positive Input
Clock2 Negative Input
Clock3 Positive Input
Clock3 Negative Input
Feedback Clock Positive Input
Feedback Clock Negative Input
Positive Differential Clock Output
Negative Differential Clock Output
Positive Differential Clock Output
Negative Differential Clock Output
Positive Differential Clock Output
Negative Differential Clock Output
Positive Differential Clock Output
Negative Differential Clock Output
Positive Differential Clock Output
Negative Differential Clock Output
Positive Differential Clock Output
Negative Differential Clock Output
Positive Differential Clock Output
Negative Differential Clock Output
Positive Differential Clock Output
Negative Differential Clock Output
Positive Differential Clock Output
Negative Differential Clock Output
Qualifier for clock input CLK3
Qualifier for clock input CLK2
Qualifier for clock input CLK1
Qualifier for clock input CLK0
selection status flag
Select PLL of static test mode
Output impedance control (high = 50 Ω)
I
I
I
I
I
Device Master Reset
2
2
2
2
2
C Interface Control, Clock
C Interface Control, Data
C Interface Control, Address 2 (MSB)
C Interface Control, Address 1
C Interface Control, Address 1 (LSB)
Description
Direction
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
I/O
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
Type
Active State
High
High
High
High
High
High
Low
Low
Advanced Clock Drivers Devices
Supply
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Freescale Semiconductor
V
V
V
V
V
V
V
V
V
V
V
V
V
DDAB
DDAB
DDAB
DDAB
DDAB
DDAB
DDAB
DDAB
DDCD
DDCD
DDCD
DDCD
DDCD
DDCD
DDCD
DDCD
DDCD
DDCD
DDIC
DDIC
DDIC
DDIC
DDIC
DDIC
DDIC
DDIC
DDIC
DDIC
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
E10
C10
D10
F10
Pin
G1
G2
D1
D2
E3
E2
C1
C2
K4
K5
K7
K6
A7
B7
A6
B6
A4
B4
A5
B5
A3
B3
E9
E8
E7
C9
A9
B8
A8
F3
F2
J4
J5
J7
J6
F8
F9

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