stlc1510 STMicroelectronics, stlc1510 Datasheet
stlc1510
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stlc1510 Summary of contents
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... G.lite DMT Transceiver LBGA132 ORDERING NUMBER: STLC1510 1.0 GENERAL DESCRIPTION The STLC1510 is a high-speed modem chip that pro- vides the digital portion of a G.992.2 DSL access at a Central Office (CO) site. It provides downstream and upstream data transport between an ATM byte stream and an analog front-end chip using Discrete Multi-Tone (DMT) Modulation ...
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... Test Access Port (TAP) This block provides the test access to the STLC1510 using JTAG and BIST techniques. HPI Interface A host processor interface is provided to allow the STLC1510 to be optionally controlled by an external microcontroller ...
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... Voltage at any 5V compatible input or output Current at any input or outputs IN OUT P Power dissipation D Vesd Electrostatic Protection I latchup I/O Latch-up Current <1> -0.8V undershoots and 6.3V overshoots do not last longer than 4nS. MINIMUM -0.5 -0.5 -40 -0.5 -0.8 1 -20 0 2000 V < 0V, V > Vdd 200 STLC1510 MAXIMUM UNITS VDD3_3 + 0 3/40 ...
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... STLC1510 Figure 2. Ball Map. 4/40 ...
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... Tol 3.3V TTL 2mA slew ltd output LinDr_AGC2 O 5V Tol 3.3V TTL 2mA slew ltd output LinDr_Peak O 5V Tol 3.3V TTL 2mA slew ltd output STLC1510 Description 17.168 MHz or 35.328 MHz reference K13 1 clock input. Hardware reset (active low) E13 ’1’ - Normal operation C13 ’ ...
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... STLC1510 Table 2. Pad Description Signal I/O Pad Type Test Interface TCK I 5V Tol CMOS input TMS I 5V Tol CMOS input TDI I 5V Tol CMOS input TDO O 5V Tol 3.3V TTL 2mA slew ltd output TRSTN I 5V Tol CMOS input Network Interface (UTOPIA / Serial Clock & Data) ...
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... Tol CMOS input/ 5V Tol 3.3V TTL 2mA slew ltd output HPI_Data_4 I/O 5V Tol CMOS input/ 5V Tol 3.3V TTL 2mA slew ltd output HPI_Data_3 I/O 5V Tol CMOS input/ 5V Tol 3.3V TTL 2mA slew ltd output STLC1510 Description Rx cell available signal Enable start of Cell P4 Utopia2 Receive data bit 7 N3 ...
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... STLC1510 Table 2. Pad Description Signal I/O Pad Type HPI_Data_2 I/O 5V Tol CMOS input/ 5V Tol 3.3V TTL 2mA slew ltd output HPI_Data_1 I/O 5V Tol CMOS input/ 5V Tol 3.3V TTL 2mA slew ltd output HPI_Data_0 I/O 5V Tol CMOS input/ 5V Tol 3.3V TTL 2mA slew ltd output HPI_Addr_2 I 5V Tol. CMOS input ...
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... VSS_20 P common ground supply pad VSS_19 P common ground supply pad VSS_18 P common ground supply pad VSS_17 P common ground supply pad STLC1510 Description General Purpose I/O Ports/ N12 D950_IDLE General Purpose I/O Ports/ P12 D950_SNAP General Purpose I/O Ports/ N11 D950_INCYCLE General Purpose I/O Ports/ P11 ...
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... STLC1510 Table 2. Pad Description Signal I/O Pad Type VSS_16 P common ground supply pad VSS_15 P common ground supply pad VSS_14 P common ground supply pad VSS_13 P common ground supply pad VSS_12 P common ground supply pad VSS_11 P common ground supply pad VSS_10 P common ground supply pad ...
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... Utopia Level 2 Physical Interface (U2PHY) and a clock and data se- rial interface (CDIF). It communicates with the rest of the STLC1510 via the Lamba Bus. Figure 3. shows a functional/data path block diagram of the NIF (this di- agram does not include all glue logic between the major functional blocks) ...
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... TxParity The following tasks are performed by the ATM net- work (in accordance with ITU-T Recommendation I.432.1), and therefore do not have to be implement the STLC1510 when using the CDIF: HCS generation (Tx). Payload scrambling (Tx). Optionally, enables clear channel mode, in which HCS generation and payload scrambling are disabled (Tx) ...
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... ATM cell boundaries) at the U-C interface. Interfaces to the Lamba bus. 5.2 FIFO The STLC1510 incorporates 4 FIFO buffers for rate decoupling: Utopia TX FIFO (8 bit input from the Utopia TX interface, 16 bit output to the ATM-TC cell processor): 243 words X 16 bits/word = 486 bytes > ...
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... STLC1510 Software programmable generation of the flag TX_CLAV (CeLl AVailable, TX direction) via registers. This translates to the FIFO having a software programmable depth. Software programmable generation of the flag TX_BP (Back Pressure, TX direction) via registers. This allows the FIFO to throttle incoming data flow, while still accepting data that was already en route when the flag was asserted ...
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... Bus Architecture (AMBA): Advanced System Bus (ASB) Advanced Peripheral Bus (APB) connected to the ASB via an APB Bridge The LAMBA Bus, a subset of the AMBA bus specifi- cation, connects all the blocks in the data pump por- tion of the STLC1510. Bridge / Arbiter/ LA MBA BUS Dec ...
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... STLC1510 5.5.1 EPM Attributes It provides access to internal registers for control and monitoring of the various hardware blocks. Provides control to perform Software (SW) download into the EPM and BPU memories as part of the power up sequence. Provides interrupt and exception handling for various macro blocks. Software on the EPM preforms several DSP functions that are not implemented in the BPU during Start-up, fast re-train or Show Time ...
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... T H PI_D ATA_ IN [7:0] P Inp essa ffer H P I_D ATA_O U T I_D ATA_O EN O utp u t Int PI_C utp Sta tus STLC1510 17/40 ...
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... STLC1510 5.7.1 Send Message from Host Processor to ARM Read Input Status Register. If h01, the ARM has not read out the last message. If h00, the ARM has read the last message and the Input Message Buffer is available for use. Clear Input Index Reg by writing any value to its address (b’ ...
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... SNR calculation - recursive average add/remove cyclic prefix Slicer Auto Correlation FDEQ update Digital AGC DATA EM DATA ( PORT ARITHMETIC UNIT (AU) AU CONTROL ADDRESS CALCULATION UNIT (ACU) PROGRAM CONTROL UNIT (PCU) AU CONTROL PROGRAM MEMORY ADDRESS PROGRAM MEMORY STLC1510 PORT PROGRAM MEMORY DATA 19/40 ...
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... STLC1510 5.9 Digital Front End (DFE) The Digital Front End (DFE) block contains dedicated hardware to map signals between the analog inter- face (AFE) and the BPU. The DFE block has the following features: It performs part of the sampling rate conversion between the AFE sampling rate and the 2x symbol rate of the BPU ...
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... The NIFTX_CLK and NIFRX_CLK are generated when the NIF is in clock and data mode, i.e. not uto- pia mode. 5.10.1RESET Structure The RESET structure for the STLC1510 has the fol- lowing requirements/attributes: Table 5. Power Mode Pin Definition PMODE[1:0] Mode State ...
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... TRSTN P9 See “RESET Structure” on page 21. 5.11.2General Purpose I/O (GPIO) Interface The STLC1510 has a 8-bit General Purpose I/O port Figure 8. GPIO Interface Block Diagram 22/40 to allow low speed control and monitoring of external signals via the LAMBA bus. The block diagram for this interface is shown in Figure 8 ...
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... The following table identifies the general DC charac- teristics for input and output pins. Conditio ns Min Typ 2 2mA 2mA 2 = =VD3_3 i Vi=VDD5 V = VDD3_3 - VDD5 100 VDD2_5 50 STLC1510 UNITS Max Unit 0 0 1.0 A 2.0 A 4 23/40 ...
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... STLC1510 7.2 AC Characteristics 7.2.1 AFE Interface Timing Figure 9. AFE Data Interface Timing (TTL Table 9. AFE Data Interface Timing Pin Name Parameter TxSOUT[1:0] tacc TxSIN[1:0] tse TxSIN[1:0] tho AS_CLK tse AS_CLK tho ...
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... Table 10. AFE Control Interface Timing Pin Name Parameter SPI_ENB tacc SPI_DTX tacc SPI_DRX tse SPI_DRX tho tac c tse th o Min. Max. 0 5ns w.r.t. rising SPI_CLK 0 5ns w.r.t. rising SPI_CLK 5ns w.r.t. falling SPI_CLK 5ns w.r.t falling SPI_CLK STLC1510 Reference Pin 25/40 ...
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... STLC1510 Figure 11. Line Driver Control Interface Timing (TTL Table 11. Line Driver Control Interface Timing Pin Name Parameter LinDr_CTRL1 tacc LinDr_CTRL2 tacc LinDr_AGC tacc 26/ Min. Max. ...
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... Table 12. Test Interface Timing Pin Name Parameter TDO tacc TDI tse TDI tho TRSTN tse TRSTN tho tse th o tse th o Min. Max. Reference Pin 0 10ns w.r.t. rising TCK 5ns w.r.t. rising TCK 5ns w.r.t rising TCK 5ns w.r.t. rising TCK 5ns w.r.t rising TCK STLC1510 27/40 ...
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... STLC1510 Network Interface Timing Figure 13. UTOPIA Transmit Interface Timing : [4 ity Table 13. Transmit Utopia Interface Timing Pin Name Parameter TxClav tacc TxSOC tse TxSOC ...
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... URxData[7:0] tacc RxAddr[4:0] tse RxAddr[4:0] tho RxParity tacc tho Min. Max. Reference Pin 0 10ns w.r.t. rising RxClk 5ns w.r.t. rising RxClk 2ns w.r.t rising RxClk 0 10ns w.r.t. rising RxClk 0 10ns w.r.t rising RxClk 5ns w.r.t. rising RxClk 2ns w.r.t. rising RxClk 5ns w.r.t. rising RxClk STLC1510 29/40 ...
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... STLC1510 Figure 15. Serial Transmit Interface Timing Table 15. Transmit Serial Interface Timing Pin Name Parameter TxClk frequency UTxData[0] tse UTxData[0] tho Figure 16. Serial Receive Interface Timing Table 16. Receive Serial Interface Timing Pin Name ...
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... HPI_BS 0.01ns w.r.t. falling HPI_CSN 10ns w.r.t. falling HPI_CSN LAMBA Bus Clock is made available on a configured output pin GPIO[0]. For timing characterization, this mode should be used to exercise the GPIO[7:1] pins as both inputs and outputs. The diagram below refers to this special mode. STLC1510 31/40 ...
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... Bits are sampled by STLC1510 on the rising edge of Tx- Clk. In the presence of clock gapping (which is gen- erated by the STLC1510 supplies the clocks in both directions), a previous bit persists until the next rising edge of the clock. Figure 21. shows the rela- tionship between TxClk and UTxData[0] ...
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... There are 5 address lines for each of the TX and RX interfaces addresses are supported, with the 32nd address (11111) being a reserved, idle address. Single PHY operation is supported by leaving the address lines set to the address of the PHY device. For more information, please see the ATM STLC1510 B (5) B (4) X B(5 ) 33/40 ...
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... MPHY port transfers data. The ATM layer polls the TxClav status of a MPHY port by placing its address on TxAddr. The MPHY port (STLC1510 device) drives TxClav during each cycle following one with its address on the TxAddr lines. Figure 23. UTOPIA Level 2 transmit timing, polling phase and selection phase. ...
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... MPHY port transfers data. The ATM layer polls the RxClav status of a MPHY port by placing its address on RxAddr. The MPHY port (STLC1510 device) drives RxClav during each cycle following one with its address on the Figure 24. UTOPIA Level 2 receive timing, polling phase and selection phase. ...
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... HP I_R PI_D ata [7:0] 36/40 8.3 Host Processor Interface (HPI) A host processor interface is provided to allow the STLC1510 to be controlled by an external microcon- troller. The design has been optimized for the Motor- ola MPC850. More details are provided in the EPM section of this document. Extern al ...
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... The format for the serial interface is given below: R/W - determines the access mode for the register address[b1:b0] . ADDR[b2:b0] - identifies the control register accessed. These registers will correspond to the mapping in the LAVA ASIC. WR_DATA[b7:b0] - the control data written to the AFE ASIC. STLC1510 37/40 ...
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... STLC1510 Figure 28. AFE Control Interface Timing Diagram 38/ ATA { ...
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... CORNER INDEX AREA (SEE NOTE.3) BOTTOM VIEW OUTLINE AND MECHANICAL DATA MAX. 0.067 0.021 0.478 0.478 Body 1.7mm 0.034 0.037 LFBGA132 0.004 (132 BALLS) STLC1510 SETING C PLANE ddd C 7146828 39/40 ...
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... STLC1510 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice ...