stlc1510 STMicroelectronics, stlc1510 Datasheet - Page 33

• Manufacturer Part Number: stlc1510
• Description: Northenlite G.lite Dmt Transceiver
• Manufacturer: STMicroelectronics

Figure 20. Network Serial Interface Tx Timing
In the Rx direction, the most significant bit of a data
byte is transmitted to the network first, with the least
significant bit transmitted last. The serial data stream
is sampled by the network on the rising edge of Rx-
Figure 21. Network Serial Interface Rx Timing
Figure 22. The NIF Utopia Level 2 Interface
N etw ork
(ATM
L ay er)
U T x Data[0 ]
Tx Clk
UR x D ata[0]
Rx Clk
B (1 )
U Tx Data[7:0]
Tx A ddr[4:0]
R xA ddr[4 :0]
T x Clav
T x BP
U R x Data[7:0]
R x S O C
R x P arity
R x C la v
Tx C lk
Tx E nb
Tx S O C
Tx P arity
R x Enb
R x Clk
B(1 )
B(0 )
S TLC 1510
(M PH Y
L ay er)
B(0 )
X
B (7 )
Clk. Samples at the gapped positions are ignored.
Figure 21. illustrates the Rx timing diagram of the se-
rial interface. Ignored samples are indicated by ’X’ in
the timing diagram.
8.2 UTOPIA Level 2 Interface
The Utopia Level 2 Interface is an 8-bit interface, op-
erating independently in the TX and RX directions.
The Utopia Level 2 Interface is briefly illustrated in
Figure 22.
General features:
B(7 )
Implemented according to The ATM Forum
Technical Committee’s Utopia Level 2
specification. Utopia Level 2 is an extension of
Utopia Level 1 which provides for connecting
multiple MPHY layer devices to a single ATM
layer. Once a given MPHY layer device has
been selected for data transfer according to the
mechanisms specified in Utopia Level 2, the
transfer itself is performed according to the
mechanisms specified in Utopia Level 1.
8-bit data transfer in each direction (TX and
RX), with a maximum clock speed of
approximately 21 MHz.
Clocks are provided by the ATM layer through
the TxClk and RxClk ports. (ATM layer is the
master, PHY layer is the slave)
There are 5 address lines for each of the TX and
RX interfaces. Up to 31 addresses are
supported, with the 32nd address (11111) being
a reserved, idle address. Single PHY operation
is supported by leaving the address lines set to
the address of the PHY device.
For more information, please see the ATM
B(6 )
B( 6)
X
X
B (5)
B(5 )
STLC1510
B (4)
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