stlc1510 STMicroelectronics, stlc1510 Datasheet - Page 18

• Manufacturer Part Number: stlc1510
• Description: Northenlite G.lite Dmt Transceiver
• Manufacturer: STMicroelectronics

STLC1510
5.7.1 Send Message from Host Processor to
5.7.2 Receive Message from ARM by Host
After receiving interrupt from ARM:
Table 3. Signal List
18/40
BRESn
BCLK
PSEL_HPI
PADDR[10:1]
PD_W[7:0]
PD_R[15:0]
PWRITE
PENABLE
HP2ARM_INT
HPI_CLK
HPI_CSN
HPI_ASN
HPI_RWN
HPI_ADDR[2:0]
HPI_DATA_IN [7:0]
HPI_DATA_OUT [7:0]
HPI_DATA_OEN
ARM2HP_INT
Read Input Status Register. If h01, the ARM has
not read out the last message. If h00, the ARM
has read the last message and the Input
Message Buffer is available for use.
Clear Input Index Reg by writing any value to its
address (b’100).
Write message into Input Message Buffer by
consecutively writing to its address (b’111). Each
write will cause the Input Index Register to
increment by 1 and access another byte location.
Write h01 to Input Status Register (address
b’011) to interrupt the ARM
Clear Output Index Register (address b’001) by
writing any value.
Read message from Output Message Buffer by
consecutively reading from its address (b’110).
Each read will cause the Output Index Register to
ARM
Processor
Name
I
I
I
I
I
O
I
I
O
I
I
I
I
I
I
O
O
O
I/O
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
External
External
External
External
External
External
External
External
External
Internal/
External
APB
APB
APB
APB
APB
APB
APB
APB
APB
HP
HP
HP
HP
HP
HP
HP
HP
HP
I/F
APB read data
Active low master RESET
ASB clock
Active high block select from APB
APB address [11:1]
APB write data
APB Write - Active high, Read - Active low
APB enable signal for timing
Interrupt from Host Processor to ARM
Host Processor bus clock
Active low select from Host Processor
Address Strobe from Host Processor
HP Read - Active high, Write - Active low
Host Processor address
Host Processor data in
Host Processor data out
Host Processor data output enable
Interrupt from ARM to Host Processor
5.7.3 Receive Message from Host Processor
After receiving interrupt from HP:
increment by 1 and access another byte location.
Clear the Output Status Reg (address b’000) by
writing any value (the ARM can clear the OSR
by writing 0 to it).
Send Message from ARM to Host Processor
Read Output Status Register. If h0001, the HP
has not read out the last message. If h0000, the
HP has read the last message and the Output
Message Buffer is available for use.
Write message into Output Message Buffer.
This buffer is directly addressable by the ARM.
Write h0001 to Output Status Register to
interrupt the HP
Read message from Input Message Buffer. This
buffer is directly addressable by the ARM.
Clear the Input Status Reg by writing h0001 to its
address (the HP can clear the ISR by writing 0 to it).
by ARM
Description