stlc1510 STMicroelectronics, stlc1510 Datasheet - Page 21

• Manufacturer Part Number: stlc1510
• Description: Northenlite G.lite Dmt Transceiver
• Manufacturer: STMicroelectronics

5.10 Timing Generation Block (TGB)
The timing and reset generation block generates the
device’s global clock and synchronization
It uses the input clock signal (35.328 or 17.664 MHz)
to derive the main internal clock signals, as well as all
synchronization pulses required to coordinate timing
between the sub-blocks. It also synchronizes the ex-
ternal RESETN with the internal ASIC clock.
The PLL input source, and PLL bypass signals are de-
coded from the PMode[1:0] pins. The CMode[1:0] pins
are configured to always provide an 8.8 MHz input to the
PLL when the PLL is not in bypass mode. Thus a divide
by 2 or 4 will be selected to divide down the 17 or 35
MHz input clock references to 8.8 MHz. When the PLL
is to be bypassed, it is powered down, and the input ref-
erence is used to bypass the PLL output.
The CK35M signals are generated by dividing down
the internal ASIC clock. A 3 bit memory mapped reg-
ister is used to adjust the reset phase of the divide by
6 generator. This gives software control of the phase
of the CK35M signal which interfaces to the AFE de-
vice. There is also a programmable ”one shot” mode
which is used to reset the phase of the CK35M in the
event the interface cannot synchronously meet the
timing requirements.
The NIFTX_CLK and NIFRX_CLK are generated
when the NIF is in clock and data mode, i.e. not uto-
pia mode.
5.10.1RESET Structure
The RESET structure for the STLC1510 has the fol-
lowing requirements/attributes:
Table 5. Power Mode Pin Definition
Table 6. Clock Mode Pin Definition
CMODE[1:0]
PMODE[1:0]
1X
00
01
10
11
00
01
Power Down Mode 0
Power Down Mode 1
Power Down Mode 2
Power Down Mode 3
Div2
Normal
Bypass
Mode State
Mode State
Nothing is powered down.
ARM7 is powered down.
D950 is powered down.
BPU processor is powered down
Master clock is REFCLK divided by 2 and then multiplied by 24. The
input REFCLK should be 17.664 MHz
Master clock is REFCLK divided by 4 and then multiplied by 24. The
input REFCLK should be 35.328 MHz
Master clock is REFCLK
signals.
5.11 Test Access Port Functional Description
The IEEE 1149.1 compliant Test Access Port (TAP)
serves three purposes:
In addition to these functions, there are two sets of
mode pins, PMODE[1:0 ], and CMODE[1:0] which
are used to put the STLC1510 into various modes.
The definition of these modes are given below, where
the shaded rows indicate special modes not to be
used in normal operations.
Requires off-chip power supervisor to supply
10ms power-on reset (may also require push
button reset for test) and 5ms TRSTN (TAP
reset).
Reset initialization will begin when RESETN is
de-asserted by the off-chip power supervisor.
After 2 rising edges of 4.4MHz clock,
ASIC_RESETn is de-asserted and the
STLC1510 (minus the BPU and D950 cores) will
come out of reset. The ARM7 will follow its boot
procedure which at some point, will download
program code to the BPU and D950 cores then
release them individually from reset.
TAP interface for both ASIC and board level
testing
RAMBIST interface for testing the embedded
memories during ASIC level test.
General Purpose I/O port for general and
miscellaneous control and monitoring.
Description
Description
STLC1510
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