stlc1510 STMicroelectronics, stlc1510 Datasheet - Page 17

• Manufacturer Part Number: stlc1510
• Description: Northenlite G.lite Dmt Transceiver
• Manufacturer: STMicroelectronics

Figure 5. HPI Block Diagram
A status register, an index register (for the Host
Processor), an interrupt mask register, and a
message buffer are required for both input and
output transactions.
The Input Status Register (ISR) is set by the
Host Processor by writing h01 and cleared by
writing h00 to the location. It is cleared by ARM
by writing anything to it.
The Output Status Registers (OSR) is set by the
ARM by writing h01 and cleared by writing h00.
It is cleared by the Host Processor by writing
anything to it.
The Input and Output Index Registers (IIR &
OIR respectively) are reset to their starting
value by writing h00 to their respective
addresses. They can also be cleared by the
Host Processor by writing anything to them.
The Input Interrupt Mask Register (IIM) resets to
h00, causing the Mask to be set (active low).
This means that before the ARM can receive
message ready interrupts from the Host
Processor, this register must be written with
B C LK
BR ESn
PS EL _ H PI
PW R ITE
PE N AB L E
PA D D R [1 0:1 ]
PD _W [7 :0]
PD _R [1 5 :0]
To /F ro m
H P I2AR M_ IN T
A R M
A
P
B
S
A
V
E
L
R e a d/W rite
O u tput S tatus R e g
O utp u t In d e x R e g
In p ut Sta tus R e g
R ea d
O utp u t Int M a sk
In pu t In de x R eg
Inp u t M essa g e
Inp u t In t M ask
2 56 B ytes
Me ssa ge
2 5 6 Bytes
O u tput
Buffer
Bu ffer
R e ad /W rite
R e a d
h0001 (by ARM) to unmask the interrupt.
The Output Interrupt Mask Register (OIM)
resets to h00, causing the Mask to be set (active
low). This means that before the Host Processor
can receive message ready interrupts from the
ARM, this register must be written with h01 (by
the Host Processor) to unmask the interrupt.
The Input and Output Message buffers are each
256 bytes long and 1 byte wide (an overflow in
the index register will not write to the other
message buffer, but will start to overwrite the
current message buffer).
Addressing of the Input and Output Message
Buffers by the Host Processor is implemented
indirectly via the Input and Output Index
Registers.
An external interrupt signal is generated when
the output status register is set by the ARM7. An
ARM7 interrupt signal is generated when the
input status register is set by the Host
Processor.
H
P
C
N
R
T
L
H PI_A D D R [2:0]
H PI_D ATA_ IN [7:0]
H P I_D ATA_O U T[7 :0 ]
H P I_D ATA_O EN
H PI_C SN
H PI_R W N
H PI_A SN
H PI_C L K
To /F ro m
AR M 2H P_ INT
H P I
STLC1510
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