stlc1510 STMicroelectronics, stlc1510 Datasheet - Page 35

• Manufacturer Part Number: stlc1510
• Description: Northenlite G.lite Dmt Transceiver
• Manufacturer: STMicroelectronics

The TxBP pin is not part of the Utopia Level 2 speci-
fication, but its functionality does not interfere with
the operation of the Utopia Level 2 Interface. It can be
left unconnected if necessary for a given application.
This signal is described in more detail in the NIF
chapter of this document.
Features of MPHY Layer Cell-Level Handshake (Rx
Direction):
Figure 24. UTOPIA Level 2 receive timing, polling phase and selection phase.
U R x D ata
R x A d dr
R x C lav
Rx C lk
R x S O C
A single MPHY port at a time is selected for a
cell transmission. However, another MPHY port
may be polled for its RxClav status while the
selected MPHY port transfers data. The ATM
layer polls the RxClav status of a MPHY port by
placing its address on RxAddr. The MPHY port
(STLC1510 device) drives RxClav during each
cycle following one with its address on the
R x E nb
C ell tran sm iss io n from :
P40
1F
P41
N -1
N -1
P H Y N
P42
polling
1F
N + 3
P43
N +3
P44
1F
P45
N + 1
N +1
P46
1F
Figure 24. illustrates the timing diagram of the re-
ceive interface when a cell is received from PHY N
and the other PHYs are polled.
RxAddr lines.
The ATM selects an MPHY port for transfer by
placing the desired MPHY port address onto
RxAddr, when RxEnb is deasserted (high)
during the current clock cycle and asserted
(low) during the following clock cycle. All MPHY
devices examine the value on RxAddr for
selection purposes when RxEnb is deasserted
(high). The MPHY port is selected starting from
the cycle after its address is on the RxAddr
lines, and RxEnb is deasserted (low); and
ending in the cycle a new MPHY port is
addressed for selection, and RxEnb is
deasserted (high).
P47
N
N
P48
se le c tio n
1F
N + 3
N +3
H 1
1F
H2
N +1
P H Y N + 3
pollin g
N +1
H3
1F
STLC1510
H4
N -1
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