adc1210s125hn/c1 NXP Semiconductors, adc1210s125hn/c1 Datasheet - Page 22

• Manufacturer Part Number: adc1210s125hn/c1
• Description: Single 12-bit Adc; 65 Msps, 80 Msps, 105 Msps Or 125 Msps; Cmos Or Lvds Ddr Digital Outputs
• Manufacturer: NXP Semiconductors

NXP Semiconductors
ADC1210S_SER_1
Preliminary data sheet
11.5.3 Data valid (DAV) output clock
11.5.4 Out-of-Range (OTR)
11.5.5 Digital offset
11.5.6 Test patterns
Table 14.
A data valid output clock signal (DAV) can be used to capture the data delivered by the
ADC1210S. Detailed timing diagrams for CMOS and LVDS DDR modes are shown in
Figure 4
An out-of-range signal is provided on pin OTR. The latency of OTR is fourteen clock
cycles. The OTR response can be speeded up by enabling Fast OTR (bit FASTOTR = 1;
see
Fast OTR detection threshold (below full-scale) can be programmed via bits
FASTOTR_DET[2:0].
Table 15.
By default, the ADC1210S delivers output code that corresponds to the analog input.
However it is possible to add a digital offset to the output code via the SPI (bits
DIG_OFFSET[5:0]; see
For test purposes, the ADC1210S can be configured to transmit one of a number of
predefined test patterns (via bits TESTPAT_SEL[2:0]; see
can be defined by the user (TESTPAT_USER; see
when TESTPAT_SEL[2:0] = 101. The selected test pattern will be transmitted regardless
of the analog input.
LVDS_INT_TER[2:0]
000
001
010
011
100
101
110
111
FASTOTR_DET[2:0]
000
001
010
011
100
101
110
111
Table
and
29). In this mode, the latency of OTR is reduced to only four clock cycles. The
LVDS DDR output register 2
Fast OTR register
Figure 5
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respectively.
Rev. 01 — 9 April 2010
Table
25).
ADC1210S series; CMOS or LVDS DDR digital outputs
Resistor value (Ω)
no internal termination
300
180
110
150
100
81
60
Detection level (dB)
−20.56
−16.12
−11.02
−7.82
−5.49
−3.66
−2.14
−0.86
Table 27
ADC1210S series
Table
and
26). A custom test pattern
Table
28) and is selected
© NXP B.V. 2010. All rights reserved.
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