adc1210s125hn/c1 NXP Semiconductors, adc1210s125hn/c1 Datasheet - Page 27
adc1210s125hn/c1
Manufacturer Part Number
adc1210s125hn/c1
Description
Single 12-bit Adc; 65 Msps, 80 Msps, 105 Msps Or 125 Msps; Cmos Or Lvds Ddr Digital Outputs
Manufacturer
NXP Semiconductors
Datasheet
1.ADC1210S125HNC1.pdf
(36 pages)
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NXP Semiconductors
Table 20.
Table 21.
ADC1210S_SER_1
Preliminary data sheet
Bit
7
6 to 4
3 to 2
1 to 0
Bit
7 to 5
4
3
2
1
0
Symbol
-
SE_SEL
DIF_SE
-
CLKDIV
DCS_EN
Symbol
SW_RST
RESERVED[2:0]
-
OP_MODE[1:0]
Reset and operating mode control register (address 0005h) bit description
Clock control register (address 0006h) bit description
Access
R/W
R/W
R/W
R/W
Access
R/W
R/W
All information provided in this document is subject to legal disclaimers.
Value
000
0
1
0
1
0
0
1
0
1
Value
0
1
000
00
00
01
10
11
Rev. 01 — 9 April 2010
Description
not used
single-ended clock input pin select
differential/single ended clock input select
not used
clock input divide by 2
duty cycle stabilizer
CLKM
CLKP
fully differential
single-ended
disabled
enabled
disabled
enabled
ADC1210S series; CMOS or LVDS DDR digital outputs
Description
reset digital section
reserved
not used
operating mode
no reset
performs a reset of the digital section
normal (power-up)
power-down
sleep
normal (power-up)
ADC1210S series
© NXP B.V. 2010. All rights reserved.
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