pca9541bs/03 NXP Semiconductors, pca9541bs/03 Datasheet - Page 18
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pca9541bs/03
Manufacturer Part Number
pca9541bs/03
Description
2-to-1 I2c Master Selector With Interrupt Logic And Reset
Manufacturer
NXP Semiconductors
Datasheet
1.PCA9541BS03.pdf
(43 pages)
- Current page: 18 of 43
- Download datasheet (218Kb)
NXP Semiconductors
PCA9541_5
Product data sheet
8.6 External reset
Thereafter, V
A reset can be accomplished by holding the RESET pin LOW for a minimum of t
PCA9541 registers and I
RESET input is once again HIGH. This input typically requires a pull-up resistor to V
Default states are:
•
•
•
•
PCA9541/03: default ‘no channel’ (no STOP detect)
After power-up and/or insertion of the device in the main I
connected to the downstream channel. The device is ready to receive a START
condition and its address by a master.
If either register writes to its Control Register, then the connection between the
upstream and the downstream channels is determined by the values on the Control
Registers.
I
PCA9541/01
no I
PCA9541/02 with Channel 0 connected to the downstream I
detection of a STOP on the upstream channel
no I
PCA9541/03.
2
C-bus upstream Channel 0 connected to the I
2
2
C-bus upstream channel connected to the I
C-bus upstream channel connected to the I
DD
must be lowered below 0.2 V to reset the device.
Rev. 05 — 1 October 2007
2
2-to-1 I
C-bus state machine will be held in their default states until the
2
C-bus master selector with interrupt logic and reset
2
2
2
C-bus downstream channel for the
C-bus downstream channel for the
C-bus downstream channel for the
2
C-bus, no channel will be
2
C-bus channel after
PCA9541
© NXP B.V. 2007. All rights reserved.
WL
. The
18 of 43
DD
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