pca9541bs/03 NXP Semiconductors, pca9541bs/03 Datasheet - Page 22
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pca9541bs/03
Manufacturer Part Number
pca9541bs/03
Description
2-to-1 I2c Master Selector With Interrupt Logic And Reset
Manufacturer
NXP Semiconductors
Datasheet
1.PCA9541BS03.pdf
(43 pages)
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NXP Semiconductors
PCA9541_5
Product data sheet
Fig 13. Write to the Interrupt Enable and Control registers using the Auto-Increment (AI) bit
Fig 14. Read the 3 registers using the Auto-Increment (AI) bit
(1) xx = 00: Interrupt Enable register
(2) xx = 00: Control register
(3) xx = 00: INT register
xx = 01: Control register
xx = 10: INT register
xx = 01: INT register
xx = 10: Interrupt Enable register
xx = 01: Interrupt Enable register
xx = 10: Control register
S
START condition
1 1 1 A3 A2 A1 A0 0
slave address
9.5 Bus transactions
S
START condition
1 1 1 A3 A2 A1 A0 0
Remark: If a third data byte is sent, it will not be acknowledged by the PCA9541.
Remark: If a fourth data byte is read, the first register will be accessed.
acknowledge
slave address
from slave
R/W
A
(1)
acknowledge
0 0 0 1 0 0 0 0
from slave
command code register
R/W
A
auto
increment
A
0 0 0 1 0 0 x x
acknowledge
from master
command code register
Rev. 05 — 1 October 2007
increment
access to register
xx = 00, 01, or 10
2-to-1 I
auto
A
acknowledge
from slave
(2)
acknowledge
2
C-bus master selector with interrupt logic and reset
from slave
Interrupt Enable (IE)
register
A
data
Sr
A
acknowledge
from master
re-START
condition
1 1 1 A3 A2 A1 A0 1
slave address
A
acknowledge
from slave
(3)
no acknowledge
acknowledge
from master
data control register
from slave
002aab608
(CONTROL)
R/W
condition
STOP
A
A
acknowledge
P
from slave
PCA9541
© NXP B.V. 2007. All rights reserved.
002aab607
condition
STOP
A
P
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