pca9574 NXP Semiconductors, pca9574 Datasheet - Page 8

• Manufacturer Part Number: pca9574
• Description: 8-bit I2c-bus And Smbus, Level Translating, Low Voltage Gpio With Reset And Interrupt
• Manufacturer: NXP Semiconductors

NXP Semiconductors
PCA9574_1
Product data sheet
7.5.2 Register 1 - Polarity inversion register
7.5.3 Register 2 - Bus-hold/pull-up/pull-down enable register
This register allows the user to invert the polarity of the Input port register data. If a bit in
this register is set (written with ‘1’), the corresponding Input port data is inverted. If a bit in
this register is cleared (written with a ‘0’), the Input port data polarity is retained.
Table 6.
Legend: * default value.
Bit 0 of this register allows the user to enable/disable the bus-hold feature for the I/O pins.
Setting the bit 0 to logic 1 enables bus-hold feature for the I/O bank. In this mode, the
pull-up/pull-downs will be disabled. Setting the bit 0 to logic 0 disables bus-hold feature.
Bit 1 of this register allows the user to enable/disable pull-up/pull-downs on the I/O pins.
Setting the bit 1 to logic 1 enables selection of pull-up/pull-down using Register 3. Setting
the bit 1 to logic 0 disables pull-up/pull-downs on the I/O pins and contents of Register 3
will have no effect on the I/O.
Table 7.
Legend: * default value.
Bit
7
6
5
4
3
2
1
0
Bit
7
6
5
4
3
2
1
0
Symbol
N0.7
N0.6
N0.5
N0.4
N0.3
N0.2
N0.1
N0.0
Symbol
E0.7
E0.6
E0.5
E0.4
E0.3
E0.2
E0.1
E0.0
Register 1 - Polarity inversion register (address 01h) bit description
Register 2 - Bus-hold/pull-up/pull-down enable register (address 02h) bit
description
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Rev. 01 — 15 May 2008
8-bit I
2
Value
0*
0*
0*
0*
0*
0*
0*
0*
Value
X
X
X
X
X
X
0*
0*
C-bus and SMBus, level translating, low voltage GPIO
Description
inverts polarity of Input port register data
Description
not used
allows the user to enable/disable pull-up/pull-downs
on the I/O pins
allows user to enable/disable the bus-hold feature for
the I/O pins
0 = Input port register data retained (default value)
1 = Input port register data inverted
0 = disables pull-up/pull-downs on the I/O pins and
contents of Register 3 will have no effect on the
I/O (default value)
1 = enables selection of pull-up/pull-down using
Register 3
0 = disables bus-hold feature (default value)
1 = enables bus-hold feature
PCA9574
© NXP B.V. 2008. All rights reserved.
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