adv7180 Analog Devices, Inc., adv7180 Datasheet - Page 19

• Manufacturer Part Number: adv7180
• Description: 10-bit, 4 X Oversampling Sdtv Video Decoder
• Manufacturer: Analog Devices, Inc.

GLOBAL CONTROL REGISTERS
Register control bits listed in this section affect the whole chip.
POWER-SAVING MODES
Power-Down
PDBP, Address 0x0F [2]
The digital supply of the ADV7180 can be shut down by using
the ( PWRDWN ) pin or via I
controls whether the I
priority. The default is to give the pin ( PWRDWN ) priority.
This allows the user to have the ADV7180 powered down by
default at power-up without the need for an I
When PDBD is 0 (default), the digital supply power is controlled
by the PWRDWN pin (the PWRDWN bit is disregarded).
When PDBD is 1, the PWRDWN bit, 0x0F[5], has priority
(the pin is disregarded).
PWRDWN, Address 0x0F [5]
When PDBP is set to 1, setting the PWRDWN bit switches the
ADV7180 to a chip-wide power-down mode. The power-down
stops the clock from entering the digital section of the chip,
thereby freezing its operation. No I
power-down. The PWRDWN bit also affects the analog blocks
and switches them into low current modes. The I
unaffected and remains operational in power-down mode.
The ADV7180 leaves the power-down state if the PWRDWN bit is
set to 0 (via I
PDBP must be set to 1 for the PWRDWN bit to power down
the ADV7180.
When PWRDWN is 0 (default), the chip is operational.
When PWRDWN is 1, the ADV7180 is in a chip-wide
power-down mode.
RESET CONTROL
RESET, Chip Reset, Address 0x0F [7]
Setting this bit, which is equivalent to controlling the RESET
pin on the ADV7180, issues a full chip reset. All I
are reset to their default/power-up values. Note that some
register bits do not have a reset value specified. They keep their
last written value. Those bits are marked as having a reset value
of x in the register tables (Table 103 and Table 104). After the
reset sequence, the part immediately starts to acquire the
incoming video signal.
2
C) or if the ADV7180 is reset using the RESET pin.
2
C control or the pin has the higher
2
C (PWRDWN, see below). PDBP
2
C bits are lost during
2
C write.
2
2
C interface is
C registers
Rev. B | Page 19 of 112
After setting the RESET bit (or initiating a reset via the RESET pin),
the part returns to the default for its primary mode of operation.
All I
self-clearing.
Executing a software reset takes approximately 2 ms. However,
it is recommended to wait 5 ms before any further I
performed.
The I
on the ninth clock cycle when chip reset is implemented. See
the MPU Port Description section.
When RESET is 0 (default), operation is normal.
When RESET is 1, the reset sequence starts.
GLOBAL PIN CONTROL
Three-State Output Drivers
TOD, Address 0x03 [6]
This bit allows the user to three-state the output drivers of the
ADV7180.
Upon setting the TOD bit, the P15 to P0 (P7 to P0 for the
ADV7180 LFCSP-40), HS, VS, FIELD (VS/FIELD pin for the
ADV7180 LFCSP-40), and SFL pins are three-stated.
The timing pins (HS, VS, FIELD) can be forced active via the
TIM_OE bit. For more information on three-state control, refer
to the Three-State LLC Driver and the Timing Signals Output
Enable sections.
Individual drive strength controls are provided via the
DR_STR_XX bits.
When TOD is 0 (default), the output drivers are enabled.
When TOD is 1, the output drivers are three-stated.
Three-State LLC Driver
TRI_LLC, Address 0x1D [7]
This bit allows the output drivers for the LLC pin of the
ADV7180 to be three-stated. For more information on three-
state control, refer to the Three-State Output Drivers and the
Timing Signals Output Enable sections.
Individual drive strength controls are provided via the
DR_STR_XX bits.
When TRI_LLC is 0 (default), the LLC pin drivers work
according to the DR_STR_C[1:0] setting (pin enabled).
When TRI_LLC is 1, the LLC pin drivers are three-stated.
2
C bits are loaded with their default values, making this bit
2
C master controller receives a no acknowledge condition
ADV7180
2
C writes are