adv7180 Analog Devices, Inc., adv7180 Datasheet - Page 63

• Manufacturer Part Number: adv7180
• Description: 10-bit, 4 X Oversampling Sdtv Video Decoder
• Manufacturer: Analog Devices, Inc.

VPS/PDC/UTC/GEMSTAR
The readback registers for VPS, PDC, and UTC are shared.
Gemstar is a high data rate standard and is available only
through the ancillary stream. However, for evaluation purposes,
any one line of Gemstar is available through the I
sharing the same register space as PDC, UTC, and VPS.
Therefore, only VPS, PDC, UTC, or Gemstar can be read
through the I
To identify the data that should be made available in the I
registers, the user must program I
(Register Address 0x9C, User Sub Map).
I
User Sub Map
Specifies which standard result is available for I
GS_PDC_VPS_UTC_CLEAR, GS/PDC/VPS/UTC Clear,
Address 0x78 [4], User Sub Map, Write Only, Self-Clearing
1—Reinitializes the GS/PDC/VPS/UTC data readback registers.
GS_PDC_VPS_UTC_AVL, GS/PDC/VPS/UTC Available,
Address 0x78 [4], User Sub Map, Read Only
0—One of GS, PDC, VPS, or UTC data was not detected.
1—One of GS, PDC, VPS, or UTC data was detected.
VDP_GS_VPS_PDC_UTC, Readback Registers,
Addresses 0x84 to 0x87
See Table 81.
VPS
The VPS data bits are biphase decoded by the VDP. The
decoded data is available in both the ancillary stream and in the
I
VDP_GS_VPS_PDC_UTC_0 to VDP_VPS_PDC_UTC_12
registers (Address 0x84 to Address 0x90, User Sub Map). The
GS_VPS_ PDC_UTC_AVL bit is set if the user programmed
I
GEMSTAR
The Gemstar-decoded data is made available in the ancillary
stream, and any one line of Gemstar is also available in the I
registers for evaluation purposes. To read Gemstar results
through the I
I
Table 80. I
I
00 (default)
01
10
11
2
2
2
2
2
C_GS_VPS_PDC_UTC[1:0]
C readback registers. VPS decoded data is available in the
C_GS_VPS_PDC_UTC to 01, as explained in Table 80.
C_GS_VPS_PDC_UTC to 00, as explained in Table 80.
C_GS_VPS_PDC_UTC [1:0] (VDP), Address 0x9C [6:5],
2
C_GS_VPS_PDC_UTC[1:0] Function
2
2
C at a time.
C registers, the user must program
2
C_GS_VPS_PDC_UTC[1:0]
Description
Gemstar 1×/2×
VPS
PDC
UTC
2
C readback.
2
C registers
2
C
Rev. B | Page 63 of 112
2
C
VDP supports autodetection of the Gemstar standard, either
Gemstar 1× or Gemstar 2×, and decodes accordingly. For the
autodetection mode to work, the user must set the
AUTO_DETECT_GS_TYPE I
Sub Map) and program the decoder to decode Gemstar 2× on
the required lines through line programming. The type of
Gemstar decoded can be determined by observing the
GS_DATA_TYPE bit (Register 0x78, User Sub Map).
AUTO_DETECT_GS_TYPE, Address 0x61 [4], User
Sub Map
0 (default)—Disables autodetection of Gemstar type.
1—Enables autodetection of Gemstar type.
GS_DATA_TYPE, Address 0x78 [5], User Sub Map,
Read Only
Identifies the decoded Gemstar data type.
0—Gemstar 1× mode is detected. Read 2 data bytes from 0x84.
1—Gemstar 2× mode is detected. Read 4 data bytes from 0x84.
The Gemstar data that is available in the I
from any line of the input video on which Gemstar was
decoded. To read the Gemstar data on a particular video line,
the user should use the manual configuration described in
Table 66 and Table 67 and enable Gemstar decoding only on the
required line.
PDC/UTC
PDC and UTC are data transmitted through Teletext Packet 8/30
Format 2 (Magazine 8, Row 30, Design Code 2 or 3), and Packet
8/30 Format 1 (Magazine 8, Row 30, Design Code 0 or 1). Thus,
if PDC or UTC data is to be read through I
teletext standard (WST or PAL System B) should be decoded by
VDP. The whole teletext decoded packet is output on the ancillary
data stream. The user can look for the magazine number, row
number, and design code and qualify the data as PDC, UTC, or
neither of these.
If PDC/UTC packets have been identified, Byte 0 to Byte 12 are
updated to the GS_VPS_PDC_UTC_0 to VPS_PDC_UTC_12
registers, and the GS_VPS_PDC_UTC_AVL bit is set. The full
packet data is also available in the ancillary data format.
Note that the data available in the I
status of the WST_PKT_DECODE_DISABLE bit (Bit 3,
Subaddress 0x60, User Sub Map).
2
C bit (Register 0x61, User
2
C register depends on the
2
2
C register could be
C, the corresponding
ADV7180