adv7180 Analog Devices, Inc., adv7180 Datasheet - Page 50

no-image

adv7180

Manufacturer Part Number
adv7180
Description
10-bit, 4 X Oversampling Sdtv Video Decoder
Manufacturer
Analog Devices, Inc.
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
adv7180B
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Part Number:
adv7180BCP32Z
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Part Number:
adv7180BCPZ
Manufacturer:
ADI
Quantity:
1 470
Part Number:
adv7180BCPZ
Manufacturer:
AD
Quantity:
699
Part Number:
adv7180BCPZ
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Part Number:
adv7180BCPZ-REEL
Manufacturer:
HP
Quantity:
600
Company:
Part Number:
adv7180BCPZ-REEL
Quantity:
15 000
Part Number:
adv7180BCPZ-S
Manufacturer:
MAX
Quantity:
2 230
Part Number:
adv7180BCPZ-S
Manufacturer:
AD
Quantity:
9 990
Part Number:
adv7180BCPZ-S
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Part Number:
adv7180BST48Z
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Part Number:
adv7180BST48Z-RL
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Part Number:
adv7180BSTZ
Manufacturer:
AMIS
Quantity:
6 240
Part Number:
adv7180BSTZ
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Part Number:
adv7180BSTZ
Manufacturer:
ADI
Quantity:
8 000
Part Number:
adv7180BSTZ
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Company:
Part Number:
adv7180KCP32Z
Quantity:
5 000
ADV7180
SYNC PROCESSING
The ADV7180 has two additional sync processing blocks that
postprocess the raw synchronization information extracted
from the digitized input video. If desired, the blocks can be
disabled via the following two I
ENHSPLL, Enable Hsync Processor, Address 0x01 [6]
The HSYNC processor is designed to filter incoming hsyncs
that have been corrupted by noise, providing improved per-
formance for video signals with stable time bases but poor SNR.
Setting ENHSPLL to 0 disables the hsync processor.
Setting ENHSPLL to 1 (default) enables the hsync processor.
ENVSPROC, Enable Vsync Processor, Address 0x01 [3]
This block provides extra filtering of the detected vsyncs to
improve vertical lock.
Setting ENVSPROC to 0 disables the vsync processor.
Setting ENVSPROC to 1(default) enables the vsync processor.
VBI DATA DECODE
There are two VBI data slicers on the ADV7180. The first is
called the VBI data processor (VDP), and the second is called
VBI System 2.
The VDP can slice both low bandwidth standards and high
bandwidth standards such as teletext. VBI System 2 can slice
low data rate VBI standards only.
The VDP is capable of slicing multiple VBI data standards on
SD video. It decodes the VBI data on the incoming CVBS and
Y/C or YUV data. The decoded results are available as ancillary
data in output 656 data stream. For low data rate VBI standards
like CC/WSS/CGMS, users can read the decoded data bytes
from I
The VBI data standards that can be decoded by the VDP are
listed in Table 63 and Table 64.
Table 63. PAL
Feature
Teletext System A, C, or D
Teletext System B/WST
Video Programming System (VPS)
Vertical Interval Time Codes ( VITC)
Wide Screen Signaling (WSS)
Closed Captioning (CCAP)
2
C registers.
2
C bits.
Standard
ITU-R BT.653
ITU-R BT.653
ETSI EN 300 231 V 1.3.1
ITU-R BT.1119-1/
ETSI EN.300294
Rev. B | Page 50 of 112
Table 64. NTSC
Feature
Teletext System B and D
Teletext System C/NABTS
Vertical Interval Time Codes (VITC )
Copy Generation Management
System (CGMS)
Gemstar
Closed Captioning (CCAP)
The VBI data standard that the VDP decodes on a particular
line of incoming video has been set by default as described in
Table 65. This can be overridden manually and any VBI data
can be decoded on any line. The details of manual
programming are described in Table 66.
VDP Default Configuration
The VDP can decode different VBI data standards on a line-to-
line basis. The various standards supported by default on
different lines of VBI are explained in Table 65.
VDP Manual Configuration
MAN_LINE_PGM, Enable Manual Line Programming of
VBI Standards, Address 0x64 [7], User Sub Map
The user can configure the VDP to decode different standards on
a line-to-line basis through manual line programming. For this,
the user has to set the MAN_LINE_PGM bit. The user needs to
write into all the line programming registers VBI_DATA_Px_Ny
(see Register 0x64 to Register 0x77 in Table 104).
0 (default)—The VDP decodes default standards on lines, as
shown in Table 65.
1—VBI standards to be decoded are manually programmed.
VBI_DATA_Px_Ny [3:0], VBI Standard to be Decoded on
Line X for PAL, Line Y for NTSC, Addresses 0x64 to 0x77,
User Sub Map
These are related 4-bit clusters in Register 0x64 to Register 0x77
of the User Sub Map. These 4-bit, line programming registers,
named VBI_DATA_Px_Ny, identify the VBI data standard that
would be decoded on Line X in PAL or on Line Y in NTSC
mode. The different types of VBI standards decoded by
VBI_DATA_Px_Ny are shown in Table 66. Note that the X or Y
value depends on whether the ADV7180 is in PAL or NTSC mode.
Standard
ITU-R BT.653
ITU-R BT.653/EIA-516
EIA-J CPR-1204/IEC 61880
EIA-608

Related parts for adv7180