adv7180 Analog Devices, Inc., adv7180 Datasheet - Page 97

• Manufacturer Part Number: adv7180
• Description: 10-bit, 4 X Oversampling Sdtv Video Decoder
• Manufacturer: Analog Devices, Inc.

Address Register
0x45
0x46
0x47
0x48
0x49
Raw Status 2
(Read Only)
Interrupt Status 2
(Read Only)
Interrupt Clear 2
(Write Only)
Interrupt Mask 2
(Read/Write)
Raw Status 3
(Read Only)
User Sub Map
Bit Description
CCAPD.
Reserved.
EVEN_FIELD.
Reserved.
MPU_STIM_INTRQ.
CCAPD_Q.
GEMD_Q.
Reserved.
SD_FIELD_CHNGD_Q.
Reserved.
Reserved.
MPU_STIM_INTRQ_Q.
CCAPD_CLR.
GEMD_CLR.
Reserved.
SD_FIELD_CHNGD_CLR.
Reserved.
Reserved.
MPU_STIM_INTRQ_CLR.
CCAPD_MSK .
GEMD_MSK .
Reserved.
SD_FIELD_CHNGD_MSK .
Reserved.
MPU_STIM_INTRQ_MSK .
SD_OP_50Hz. SD 60 Hz/50 Hz
frame rate at output.
SD_V_LOCK.
SD_H_LOCK.
Reserved.
SCM_LOCK.
Reserved.
Reserved.
Reserved.
Rev. B | Page 97 of 112
7 6 5 4 3 2 1 0
0
1
0
1
0
1
0
1
x
Bit
x x
x
x
0 0
x
(Shading Indicates
Default State)
x
x
x
0
1
0
1
0
1
0
1
0
1
x x x
x x
0 0
0 0
x
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Comments
No CCAPD data detected—
VBI System 2
CCAPD data detected—VBI System 2
Current SD field is odd numbered
Current SD field is even numbered
MPU_STIM_INT = 0
MPU_STIM_INT = 1
Closed captioning not detected in the
input video signal—VBI System 2
Closed captioning data detected in the
video input signal—VBI System 2
Gemstar data not detected in the input
video signal—VBI System 2
Gemstar data detected in the input
video signal—VBI System 2
SD signal has not changed field from
odd to even or vice versa
SD signal has changed Field from odd to
even or vice versa
Not used
Not used
Manual interrupt not set
Manual interrupt set
Do not clear—VBI System 2
Clears CCAPD_Q bit – VBI System 2
Do not clear
Clears GEMD_Q bit
Do not clear
Clears SD_FIELD_CHNGD_Q bit
Not used
Not used
Do not clear
Clears MPU_STIM_INTRQ_Q bit
Masks CCAPD_Q bit—VBI System 2
Unmasks CCAPD_Q bit—
VBI System 2
Masks GEMD_Q bit—VBI System 2
Unmasks GEMD_Q bit—VBI System 2
Not used
Masks SD_FIELD_CHNGD_Q bit
Unmasks SD_FIELD_CHNGD_Q bit
Not used
Masks MPU_STIM_INTRQ_Q bit
Unmasks MPU_STIM_INTRQ_Q bit
SD 60 Hz signal output
SD 50 Hz signal output
SD vertical sync lock not established
SD vertical sync lock established
SD horizontal sync lock not established
SD horizontal sync lock established
Not used
SECAM lock not established
SECAM lock established
Not used
Not used
Not used
Notes
These bits are status bits
only; they cannot be
cleared or masked;
Register 0x46 is used for
this purpose
These bits can be cleared
or masked by Registers
0x47 and 0x48,
respectively
Note that interrupt in
Register 0x46 for the
CCAP, Gemstar, CGMS, and
WSS data is using the
Mode 1 data slicer
Note that interrupt in
Register 0x46 for the
CCAP, Gemstar, CGMS, and
WSS data is using the
Mode 1 data slicer
Note that interrupt in
Register 0x46 for the
CCAP, Gemstar, CGMS, and
WSS data is using the
Mode 1 data slicer.
These bits are status bits
only; they cannot be
cleared or masked;
Register 0x4A is used for
this purpose
ADV7180