dac1408d650 NXP Semiconductors, dac1408d650 Datasheet
dac1408d650
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dac1408d650 Summary of contents
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... The input data format is serial according to JESD204A specification. This new interface has numerous advantages over the traditional parallel one: easy PCB layout, lower radiated noise, lower pin count, self-synchronous link, skew compensation. DAC1408D650 maximum number of lanes is 4 and its maximum serial data rate is 3.25 Gbps. 2. Features ...
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... I Description plastic thermal enhanced thin quad flat package; 100 leads; body mm; exposed die pad Rev. 01 — 26 May 2009 DAC1408D650 Industrial temperature range from +85 C Typical power dissipation: 1.19 W Power down and Sleep modes Version SOT638-1 © NXP B.V. 2009. All rights reserved. ...
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Block diagram SDO SPI CONTROL REGISTERS SYNC_OUTP DIGITAL LAYER PROCESSING SYNC_OUTN VIN_P0 LANE PROC VIN_N0 VIN_P1 LANE PROC VIN_N1 VIN_P2 LANE PROC VIN_N2 VIN_P3 LANE PROC VIN_N3 PLL CLKINP CLKINN CLKP Fig 1. Block diagram SDIO SCS_N SCLK NCO ...
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... DDD(1V8) DGND 19 n. n.c. n. n.c. Fig 2. Pin configuration DAC1408D650_1 Objective data sheet Dual 14-bit DAC 650 Msps, 2 and 4 interpolating DAC1408D650 AGND Rev. 01 — 26 May 2009 DAC1408D650 75 V DDA(3V3) 74 AUXBP 73 AUXBN 72 AGND 71 V DDA(1V8 DDA(1V8) 69 GAPOUT 68 VIRES 67 n.c. 66 RESET_N ...
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... P serial interface analog supply voltage 1 serial interface lane 1 positive input 37 I serial interface lane 1 negative input 38 G serial interface analog ground 39 I serial interface lane 2 negative input Rev. 01 — 26 May 2009 DAC1408D650 © NXP B.V. 2009. All rights reserved ...
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... DAC B output 74 O complementary auxiliary DAC B output 75 P analog supply voltage 3 analog ground 77 P analog supply voltage 1 analog ground 79 P analog supply voltage 1 analog ground Rev. 01 — 26 May 2009 DAC1408D650 © NXP B.V. 2009. All rights reserved ...
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... analog ground 95 P analog supply voltage 1 analog ground 97 P analog supply voltage 1 analog ground 99 P analog supply voltage 1.8 V 100 G analog ground [ analog ground Rev. 01 — 26 May 2009 DAC1408D650 © NXP B.V. 2009. All rights reserved ...
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... Dual 14-bit DAC 650 Msps, 2 and 4 interpolating Conditions JESD204A compliant , and V DDD DDA(PLL) DDD(PLL) DD(IO) are respected. CC Thermal characteristics Parameter thermal resistance from junction to ambient thermal resistance from junction to case Rev. 01 — 26 May 2009 DAC1408D650 Min [1] 0.5 [1] 0.5 [2] 0.5 [2] 0.5 [2] 0.5 [2] 0.5 0 may have any value between 0 ...
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... Msps interpolation; NCO on including PLL MHz; o NCO on 640 Msps; s interpolation; JESD204A compliant MHz 640 Msps interpolation; NCO on X/sin X function on Rev. 01 — 26 May 2009 DAC1408D650 = 3 3.6 V; AGND, GND(PLL), DGND and DDA(3V3 DDA(1V8) DD(PLL) [1] Test Min Typ I 1.65 1.8 I 3.0 3.3 I 1.65 1 ...
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... DAC A, DAC B and JESD204A power down DAC A and DAC B Sleep mode [2] range, CLK+ or CLK [4] V < gpd [4] V < gpd 2 Rev. 01 — 26 May 2009 DAC1408D650 = 3 3.6 V; AGND, GND(PLL), DGND and DDA(3V3 DDA(1V8) DD(PLL) [1] Test Min Typ C - tbd ...
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... L O(fs) Conditions [3] reg value = 00h reg = default value compliance range guaranteed external voltage 1.2 V compliance range guaranteed interpolation 4 interpolation serial input up to 0.5 LSB Rev. 01 — 26 May 2009 DAC1408D650 = 3 3.6 V; AGND, GND(PLL), DGND and DDA(3V3 DDA(1V8) DD(PLL) [1] Test Min Typ - 0.7 - 100 C 0.79 0.98 C ...
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... NCO on; interpolation carriers MHz 2 carriers MHz 4 carriers MHz NCO on; 2 interpolation carriers MHz 2 carriers MHz 4 carriers MHz Rev. 01 — 26 May 2009 DAC1408D650 = 3 3.6 V; AGND, GND(PLL), DGND and DDA(3V3 DDA(1V8) DD(PLL) [1] Test Min Typ D - ...
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... L O(fs) Conditions f = 640 Msps; 8 interpolation noise shaper disable noise shaper enable f _offset --------------------- - 2.715 – MHz Rev. 01 — 26 May 2009 DAC1408D650 = 3 3.6 V; AGND, GND(PLL), DGND and DDA(3V3 DDA(1V8) DD(PLL) [1] Test Min Typ = 19 MHz at 0 dBFS 154 ...
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... NXP Semiconductors 10. Application information 10.1 General description The DAC1408D650 is a dual 14-bit DAC operating up to 650 Msps. Each DAC consists of a segmented architecture, comprising a 6-bit thermometer sub-DAC and an 8-bit binary weighted sub-DAC. With a maximum input data rate 325 Msps and a maximum output sampling rate of 650 Msps, the DAC1408D650 allows more fl ...
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... Fig 3. JESD204A receiver The JEDEC204A defines the following parameters: The DAC1408D650 supports both LMF = 421 and LMF = 211. The current setting is configurable via the SPI registers interface. The complete Digital Layer Processing adds a variable delay on each lane path. This is mainly due to the inter-lane alignment. ...
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... As stated in JESD204A, transmitter and receiver have to first synchronize. This is achieved through SYNC_OUT signals and SYNC pattern (K28.5 symbol). The receiver (i.e. DAC1408D650) first drives its SYNC outputs. The SYNC signal/pattern is continuously sent until the receiver deasserts the SYNC signal. The Lane Processing makes use of the SYNC-patterns to synchronize the datastream, determine the initial running disparity and to extract the 10 bits word from the incoming datastream (word-alignment) ...
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... NXP Semiconductors The SYNC signal is also used during normal operation by the DAC1408D650 to request a link re-initialization. This occurs when the 8b/10b module loses synchronization. The SYNC_OUT signal conforms to LVDS signaling. Its common mode voltage (see 39 “Page 2 register allocation 39 “Page 2 register allocation SYNC_OUT is synchronous with the frame clock. ...
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... INVALID: a code group that either shows a disparity error or that does not exist in the 8b/10b decoding table. DAC1408D650 supports character replacement whatever the state of the descrambler. When scrambling isn’t active, the received K28.3 /A/ or K28.7 /F/ will be replaced by the previous sample. When scrambling is active, the corresponding data octet D28.3 (0xC) or D28 ...
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... NXP Semiconductors 10.2.6 Frame assembly DAC1408D650 supports only / which means that every frame clock period carries one byte per lane. Frame assembly combines the octet of lane_0 with the 6 msb bits of lane_1 and re-assemble the original 14 bits sample. The same is done for lane_2 and lane_3. Tail bits are dropped ...
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... Fig 8. Frame assembly 10.3 Serial interface (SPI) 10.3.1 Protocol description The DAC1408D650 serial interface is a synchronous serial communication port allowing easy interfacing with many industry microprocessors. It provides access to the registers that define the operating modes of the chip in both write and read modes. DAC1408D650_1 ...
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... Read or Write mode access description Description Write mode operation Read mode operation below, N1 and N0 indicate the number of bytes transferred after the instruction Number of bytes to be transferred Table 18 “Page 0 register allocation Rev. 01 — 26 May 2009 DAC1408D650 Number of bytes transferred 1 ...
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... SCLK 50 % SDIO h(SDIO) t su(SDIO) SPI timing characteristics Parameter SCLK frequency SCLK pulse width SCS_N set-up time SCS_N hold time SDIO set-up time SDIO hold time RESET_N pulse width Rev. 01 — 26 May 2009 DAC1408D650 t w(SCLK) Table 10. Min Typ Max - - ...
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... Fig 11. LVDS clock configuration Fig 12. Interfacing CML to LVDS The DAC1408D650 can operate with a clock frequency up to 325 MHz. Both clock inputs can be LVDS (see During the reset phase (RESET_N asserted), both clocks must be stable and running. This ensures proper reset of the complete device. ...
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... H(55) 4 H(54) 0 H(53) 13 H(52) 0 H(51) 34 H(50) 0 H(49) 72 H(48) 0 H(47) 138 H(46) 0 H(45) 245 H(44) 0 H(43) 408 H(42) 0 H(41) 650 H(40) 0 H(39) 1003 H(38) 0 H(37) 1521 H(36) 0 H(35) 2315 H(34) 0 H(33) 3671 H(32) 0 H(31) 6642 H(30) 0 H(29) 20756 32768 Rev. 01 — 26 May 2009 DAC1408D650 Second interpolation filter Lower Upper Value H(1) H(23) H(2) H(22) 0 H(3) H(21) 17 H(4) H(20) 0 H(5) H(19) H(6) H(18) 0 H(7) H(17) 238 H(8) H(16) 0 H(9) H(15) H(10) H(14) 0 H(11) H(13) 2530 H(12) - 4096 - - - - - - - - - - - - - - - - - - - ...
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... Dual 14-bit DAC 650 Msps, 2 and 4 interpolating ---------------- - MHz when f NCO ---------------- - 5 2 Table 12 “Inversion filter Rev. 01 — 26 May 2009 DAC1408D650 = 640 Msps and the default phase coefficients”. (1) (2) © NXP B.V. 2009. All rights reserved ...
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... O fs The output current depends on the digital input data: I IOUTP I IOUTN The setting applied to CODING (register 00h[2]; see map”) defines whether the DAC1408D650 operates with a binary input or a two’s complement input. Table 13 “DAC transfer function” when I O(fs) Table 13. Data 0 ...
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... DAC1408D650_1 Objective data sheet Dual 14-bit DAC 650 Msps, 2 and 4 interpolating shows the internal configuration. The DAC1408D650 reference circuitry configuration”). 100 nF GAPOUT AGND 910 ...
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... The coding of the fine gain adjustment is two’s complement. 10.10 Digital offset adjustment When the DAC1408D650 analog output is DC connected to the next stage, the digital offset correction can be used to adjust the common mode level at the output of the DAC. It adds an offset at the end of the digital part, just before the DAC. ...
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... Analog output The DAC1408D650 has two output channels each of which produces two complementary current outputs. These allow the even-order harmonics and noise to be reduced. The pins are IOUTAP/IOUTAN and IOUTBP/IOUTBN respectively and need to be connected via a load resistor R ...
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... NXP Semiconductors 10.12 Auxiliary DACs The DAC1408D650 integrates 2 auxiliary DACs that can be used to compensate for any offset between the DAC and the next stage in the transmission path. Both auxiliary DACs have a resolution of 10-bit and are current sources (referenced to ground AUX The output current depends on the auxiliary DAC data: ...
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... The use of a differentially-coupled transformer output provides optimum distortion performance (see helps to match the impedance and provides electrical isolation. Fig 15 The DAC1408D650 can operate recommended to connect the center tap of the transformer the 3.3 V analog power supply, in order to adjust the DC common mode to approximately 2.7 V (see Fig 16 ...
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... DC interface to an Analog Quadrature Modulator (AQM) When the system operation requires to keep the DC component of the spectrum, the DAC1408D650 can use a DC interface to connect to an AQM. In this case, the offset compensation for LO cancellation can be made with the use of the digital offset control in the DAC ...
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... V 54.9 54.9 IOUTP IOUTN 634 k 634 k AUXP AUXN 442 k 442 k IOUTP/IOUTN V = 2.75 V o(cm 1.96 V o(dif)(p-p) Rev. 01 — 26 May 2009 DAC1408D650 AQM (V i(cm) 442 BBP 442 BBN 698 698 51.1 51.1 BBP/BBN V = 1.7 V i(cm 1.23 V i(dif)(p-p) offset correction AQM when using auxiliary DACs ...
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... NXP Semiconductors 10.13.3 AC interface to an Analog Quadrature Modulator (AQM) When the AQM common mode voltage is close to ground, the DAC1408D650 must be AC-coupled and the auxiliary DACs are needed for offset correction. Figure 20 input level when using auxiliary DACs. Fig 21. An example interface ...
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... NXP Semiconductors 10.15 Configuration interface 10.15.1 Register description DAC1408D650 implements indirect addressing using a page access method. The page-address is located at address 0x1F and is by default 0x00, which selects page_0 as default-page. For example, to access registers which configure the jesdrx, one must first activate page_4 by writing 0x04 to the page-address 0x1F. ...
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Page 0 allocation map description Table 18. Page 0 register allocation map Address Register name R/W Bit definition b7 0 00h COMMON R/W SPI_3W 1 01h TXCFG R/W NCO_EN 2 02h PLLCFG R/W PD_PLL 3 03h FREQNCO_LSB R/W 4 ...
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... COMMON register (address 00h) bit description Symbol Access Value Description SPI_3W R/W SPI_RST R/W INTERLEAVED_MODE R/W DF R/W PD_ALL R/W GAP_PD R/W Rev. 01 — 26 May 2009 DAC1408D650 serial interface bus type 0 4 wire SPI 1 3 wire SPI serial interface reset 0 no reset 1 performs a reset on all registers except 0x00 state 0 disabled 1 ...
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... R Rev. 01 — 26 May 2009 DAC1408D650 NCO disabled (the NCO phase is reset to 0) enabled low-power NCO NCO may use all 32 bits NCO frequency and phase given by the five MSBs of the registers 06h and 08h respectively x / (sin x) function disabled ...
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... Symbol Access Value Description R/W FREQNCO_MSB register (address 06h) bit description Symbol Access Value Description R/W PHINCO_LSB register (address 07h) bit description Symbol Access Value Description R/W Rev. 01 — 26 May 2009 DAC1408D650 Value Description PLL 0 switched on 1 switched off undefined PLL divider 0 switched on 1 ...
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... DAC_B_CFG_1 register (address 0Ch) bit description Symbol Access Value Description DAC_B_PD R/W DAC_B_SLEEP R/W R/W DAC_B_CFG_2 register (address 0Dh) bit description Symbol Access Value Description R/W Rev. 01 — 26 May 2009 DAC1408D650 - most significant 8-bits for the NCO phase setting DAC A power off DAC A Sleep mode 0 disabled 1 enabled ...
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... AUX_B[9:2] R/W DAC_B_Aux_LSB register (address 1Dh) bit description Symbol Access Value AUX_B_PD R/W AUX_B[1:0] R/W Rev. 01 — 26 May 2009 DAC1408D650 - most significant 2-bits for the DAC B gain setting for coarse adjustment - most significant 6-bits for the DAC B offset Description NCO gain 0 unity ...
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Page 2 allocation map description Table 39. Page 2 register allocation map Address Register name R/W Bit definition 00h MAINCONTROL R 01h MAN_PON R 02h MAN_SUPD R/W MAN_PLL MAN_PLL _SEL_PD ...
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Table 39. Page 2 register allocation map …continued Address Register name R/W Bit definition 1Dh DIG_VERSION R DIG_VERSION_ID[7:0] 30 1Eh JRX_ANA_VERSI R JRX_ANA_VERSION_ID[7: 1Fh PAGE_ADDRESS R/W PAGE Default b1 b0 Bin ...
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... MAN_PON register (address 01h) bit description Symbol Access Value Description MAN_PON_CLKBUFFER R/W MAN_PON_ALL R/W MAN_PON_LN3 R/W MAN_PON_LN2 R/W MAN_PON_LN1] R/W MAN_PON_LN0 R/W Rev. 01 — 26 May 2009 DAC1408D650 initialization 1 full re-initialization 0 quick re-initialization sync 0 sync starts with '0' 1 sync starts with '1' pon 1 manual control of pon's 0 pon's jesdrx module controlled by dcsmu ...
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... PLL_RUN_IN_TIME register (address 08h) bit description Symbol Access Value Description CA_RUN_IN_TIME register (address 09h) bit description Symbol Access Value Description Rev. 01 — 26 May 2009 DAC1408D650 Value Description sel_pd_ln3 (when man_supd_cntrl = 1) sel_pd_ln2 (when man_supd_cntrl = 1) sel_pd_ln1 (when man_supd_cntrl = 1) sel_pd_ln0 (when man_supd_cntrl = 1) startup_ln3 (when man_supd_cntrl = 1) ...
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... Access Value Description R/W SET_RATIO_PD1 register (address 13h) bit description Symbol Access Value Description R/W SET_RATIO_PD2 (address 14h) bit description Symbol Access Value R/W Rev. 01 — 26 May 2009 DAC1408D650 0 I_IN <= DATA_I_CDI 1 I_IN <= DATA_I_CDI when EN_DATA_I_CDI='1' else 1X: I_IN <= IQ_DC_LEVEL Q_IN <= DATA_Q_CDI 1 Q_IN <= DATA_Q_CDI when EN_DATA_Q_CDI='1' else 1X: Q_IN < ...
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... RING_OSC_TEST R/W DES_TEST R/W DAC_TEST R/W JD_MODE R/W CDI_MODE R/W SR_CDI R/W Rev. 01 — 26 May 2009 DAC1408D650 Description - proportional chargepump pfd ( linear PLL) Description set Vcm voltage levelr Description set sync transmitter common mode level set sync transmitter outputlevel swing Description 0 normal mode (inv_sinc à dac-inputs) 1 io-bus direct mapped to dac-inputs ...
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... IO_MUX_CNTRL1 register (address 1Ch) bit description Symbol Access Value SEL_RI R/W SEL_FD R/W SEL_AD R/W SEL_CK[1:0] R/W Rev. 01 — 26 May 2009 DAC1408D650 Description MX_DCLK <= EN_DATA_I_CDI and DATA_I_CDI_0 MX_DCLK <= EN_DATA_I_CDI and DATA_I_CDI_1OFF MX_DCLK <= EN_DATA_Q_CDI and DATA_Q_CDI_0 MX_DCLK <= EN_DATA_Q_CDI and DATA_Q_CDI_1 MX_DCLK <= I_EN and I_OUT(INVSINC_I_OUT) and "00" ...
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... JRX_ANA_VERSION register (address 1Eh) bit description Symbol Access Value JRX_ANA_VERSION_ID[7:0] R/W PAGE_ADDRESS register (address 1Fh) bit description Symbol Access Value PAGE R/W Rev. 01 — 26 May 2009 DAC1408D650 Description - metalfixable version -id within digital (standard cell) Description - metalfixable version -id within analog deserializer Description ...
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Page 4 allocation map description Table 65. Page 4 register allocation map Address Register name R/W Bit definition 00h SR_DLP_0 R/W SR_SWA_ SR_SWA_ LN3 1 01h SR_DLP_1 R/W SR_CNTRL SR_CNTRL _LN3 2 02h FORCE_LOCK R/W FORCE_ ...
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Table 65. Page 4 register allocation map …continued Address Register name R/W Bit definition 12h INIT_SCR_ R/W - S7T1_LN0 19 13h INIT_SCR_ R/W S15T8_LN1 20 14h INIT_SCR_ R/W - S7T1_LN1 21 15h INIT_SCR_ R/W S15T8_LN2 22 16h ...
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... R/W Rev. 01 — 26 May 2009 DAC1408D650 softreset sync_word_alignment lane_3 softreset sync_word_alignment lane_2 softreset sync_word_alignment lane_1 softreset sync_word_alignment lane_0 0 softreset clock_alignment lane_3 1 softreset clock_alignment lane_2 softreset clock_alignment lane_1 1 softreset clock_alignment lane_0 soft reset controller lane_3 soft reset controller lane_2 ...
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... Symbol Access Value Description CA_CNTRL register (address 05h) bit description Access Value R/W R/W R/W R/W R/W R/W R/W R/W Rev. 01 — 26 May 2009 DAC1408D650 manual lock-settting sync-word-alignment lane_1 manual lock-settting sync-word-alignment lane_0 manual lock-settting sync-word-alignment lane_3 manual lock-settting sync-word-alignment lane_2 Description 0 dout_ca_ln3[7:0] = din_ca_ln3[7:0] 1 dout_ca_ln3[7:0] = din_ca_ln3[0:7] 0 dout_ca_ln2[7:0] = din_ca_ln2[7:0] 1 dout_ca_ln2[7:0] = din_ca_ln2[0:7] ...
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... Rev. 01 — 26 May 2009 DAC1408D650 Description scrambling ln3 off (when force_scr_ln3 = 1) scrambling ln3 on (when force_scr_ln3 = 1) scrambling ln2 off (when force_scr_ln2 = 1) scrambling ln2 on (when force_scr_ln2 = 1) scrambling ln1 off (when force_scr_ln1 = 1) scrambling ln1 on (when force_scr_ln1 = 1) scrambling ln0 off (when force_scr_ln0 = 1) ...
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... Symbol Access Value Description MAN_ALIGN_LN_0_1 register (address 0Ah) bit description Symbol Access Value Description Rev. 01 — 26 May 2009 DAC1408D650 Description inter-lane alignment based on ln3:ln2 and/or ln1:ln0 inter-lane alignment based on ln3:ln0 ila is done after receiving 1 /A/-symbol ila is done after receiving 2 /A/-symbols ...
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... R/W LN10[1: Rev. 01 — 26 May 2009 DAC1408D650 error_handling i.c.o. unexpected /K/ in lane error_handling i.c.o. unexpected /K/ in lane 2 and 3 error_handling i.c.o. unexpected /K/ in lane 2 error_handling i.c.o. unexpected /K/ in lane 3 error_handling i.c.o. unexpected /K/ in lane error_handling i.c.o. unexpected /K/ in lane 0 and 1 error_handling i.c.o. unexpected /K/ in lane 0 error_handling i.c.o. unexpected /K/ in lane 1 error_handling i ...
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... R/W POL_LN2 R/W POL_LN1 R/W POL_LN0 R/W Rev. 01 — 26 May 2009 DAC1408D650 i_re_init when 1 of the lane_rst's is active i_re_init when rst_ln0 or rst_ln1 is active i_re_init when rst_ln2 or rst_ln3 is active i_re_init when rst_ln0 is active i_re_init when rst_ln1 is active i_re_init when rst_ln2 is active i_re_init when rst_ln3 is active i_re_init remains '0' ...
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... SR_SCR_LN2 R/W SR_SCR_LN1 R/W SR_SCR_LN0 R/W INIT_SCR_S15T8_LN0 register (address 11h) bit description Symbol Access Value Description Rev. 01 — 26 May 2009 DAC1408D650 00 ila_in_ln3 = lane_ln0 (dout and controls) 01 ila_in_ln3 = lane_ln1 (dout and controls) 10 ila_in_ln3 = lane_ln2 (dout and controls) 11 ila_in_ln3 = lane_ln3 (dout and controls) 00 ila_in_ln2 = lane_ln0 (dout and controls) ...
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... INIT_ILA_BUFPTR_LN01 register (address 19h) bit description Symbol INIT_ILA_BUFPTR_LN1[3:0] INIT_ILA_BUFPTR_LN0[3:0] INIT_ILA_BUFPTR_LN23 register (address 1Ah) bit description Symbol INIT_ILA_BUFPTR_LN3[3:0] INIT_ILA_BUFPTR_LN2[3:0] Rev. 01 — 26 May 2009 DAC1408D650 - init value for ln0 descrambler bits s7:s1 01h init value for ln1 descrambler bits s15:s8 Access Value Description R/W - init value for ln1 descrambler bits s7:s1 ...
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... PAGE_ADDRESS register (address 1Fh) bit description Symbol Access Value PAGE R/W - Rev. 01 — 26 May 2009 DAC1408D650 Description nit-errors passed to frame-assembler (fa‘) nad(nit- and disparity)-errors passed to fa unexpected k-character errors ignored (@fa) unexpected k-character errors concealment(2fa) nad-errors ignored (@fa) nad-errors concealment (@fa) conceal 1 period @ fa ...
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Page 5 allocation map description Table 94. Page 5 register allocation map Address Register name R/W Bit definition 00h ILA_MON_1_0 R 1 01h ILA_MON_3_2 R 2 02h ILA_BUF_ERR 03h CA_MON R CA_MON_LN3[1:0] 4 ...
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Table 94. Page 5 register allocation map …continued Address Register name R/W Bit definition 16h FLAG_CNT_LSB_ R LN3 23 17h FLAG_CNT_MSB_ R LN3 25 19h BER_LEVEL R/W 26 1Ah INTR_ENA R/W INTR_EN INTR_EN A_NIT A_DISP 27 1Bh ...
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... R/W ILA_BUF_ERR_LN1 R/W ILA_BUF_ERR_LN0 R/W CA_MON register (address 03h) bit description Symbol Access R/W R/W R/W R/W Rev. 01 — 26 May 2009 DAC1408D650 ila_buf_ln1 pointer ila_buf_ln0 pointer ila_buf_ln3 pointer ila_buf_ln2 pointer Value Description 0 ila_buf_ln3 pointer is in range 1 ila_buf_ln3 pointer is out of range 0 ila_buf_ln2 pointer is in range 1 ila_buf_ln2 pointer is out of range ...
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... R/W K28_5_LN2 R/W K28_4_LN2 R/W K28_3_LN2 R/W K28_0_LN2 R/W Rev. 01 — 26 May 2009 DAC1408D650 not-in-table-errorflag lane_3 not-in-table-errorflag lane_2 not-in-table-errorflag lane_1 not-in-table-errorflag lane_0 disparity-errorflag lane_3 disparity-errorflag lane_2 disparity-errorflag lane_1 disparity-errorflag lane_0 /K/-symbols found in lane_3 /K/-symbols found in lane_2 ...
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... Symbol Access Value Description R/W Symbol Access Value Description R/W Rev. 01 — 26 May 2009 DAC1408D650 k28_7 /F/ -symbols found in lane_3 k28_5 /K/ -symbols found in lane_3 k28_4 /Q/ -symbols found in lane_3 k28_3 /A/ -symbols found in lane_3 k28_0 /R/ -symbols found in lane_3 Unexpected /K/-symbols found in lane_3 Unexpected /K/-symbols found in lane_2 ...
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... R/W Symbol Access Value Description R/W Symbol Access Value Description R/W Access Value Description R/W R/W R/W R/W Rev. 01 — 26 May 2009 DAC1408D650 lsb's of flag_counter ln2 msb's of flag_counter ln2 lsb's of flag_counter ln3 msb's of flag_counter ln3 level used for simple(dc) ber-measurement 0 no action 1 nit-error in ln<x> affects i_ln<x> action 1 disparity-error in ln<x> affects i_ln<x> ...
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... RST_DISP_ERR_FLAGS R/W RST_KOUT_FLAGS R/W RST_KOUT_UNEXPECTE R/W D_FLAGS RST_K28_LN3_FLAGS R/W RST_K28_LN2_FLAGS R/W RST_K28_LN1_FLAGS R/W RST_K28_LN0_FLAGS0 R/W Rev. 01 — 26 May 2009 DAC1408D650 …continued 0 no action 1 detection k28_5 in ln<x> affects i_ln<x> action 1 detection k28_3 in ln<x> affects i_ln<x> action 1 detection k28_0 in ln<x> affects i_ln<x> reset flagcnt ln1 select cnt-enable flagcnt ln1 (see section 4.4) reset fl ...
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... Dual 14-bit DAC 650 Msps, 2 and 4 interpolating Symbol Access Value BER_MODE R/W INTR_CLEAR R/W INTR_MODE[2:0] R/W DBG_MODE R/W Symbol Access Value PAGE R/W - Rev. 01 — 26 May 2009 DAC1408D650 Description 0 no action 1 simple BER-measurement enabled 00 no action 01 clear interrupt (to '1')s 000 intr depends on i_ln0 001 intr depends on i_ln1 010 intr depends on i_ln2 011 ...
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Page 6 allocation map description Table 123. Page 6 register allocation map Address Register name R/W Bit definition b7 0 00h LN0_CFG_0 R 1 01h LN0_CFG_1 02h LN0_CFG_2 03h LN0_CFG_3 R LN0_SCR 4 ...
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Table 123. Page 6 register allocation map …continued Address Register name R/W Bit definition b7 28 1Ch LN1_CFG_12 R 29 1Dh LN1_CFG_13 R 31 1Fh PAGE_ADDRESS R LN1_RES2[7:0] LN1_FCHK[7:0] PAGE Default Bin Hex ...
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... Access Value Description R/W Symbol Access Value LN0_K[4:0] R/W Symbol Access Value LN0_M[7:0] R/W Symbol Access Value LN0_CS[1:0] R/W LN0_N[4:0] R/W Symbol Access Value LN0_N’[4:0] R/W Rev. 01 — 26 May 2009 DAC1408D650 Value Description Value Description Description Description Description Description © NXP B.V. 2009. All rights reserved ...
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... LN1_BID[3:0] R/W Symbol Access Value LN1_LID[4:0] R/W Symbol Access Value LN1_SCR R/W LN1_L[4:0] R/W Symbol Access Value LN1_F[7:0] R/W Symbol Access Value LN1_K[4:0] R/W Rev. 01 — 26 May 2009 DAC1408D650 Description Description Description Description Description Description Description Description Description Description Description © NXP B.V. 2009. All rights reserved ...
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... Access Value LN1_HD R/W LN1_CF[4:0] R/W Symbol Access Value LN1_RES1[7:0] R/W Symbol Access Value LN1_RES2[7:0] R/W Symbol Access Value LN1_FCHK[7:0] R/W Symbol Access Value PAGE R/W - Rev. 01 — 26 May 2009 DAC1408D650 Description Description Description Description Description Description Description Description Description page_address © NXP B.V. 2009. All rights reserved ...
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Page 7 allocation map description Table 153. Page 7 register allocation map Address Register name R/W Bit definition b7 0 00h LN2_CFG_0 R 1 01h LN2_CFG_1 02h LN2_CFG_2 03h LN2_CFG_3 R LN2_SCR 4 ...
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Table 153. Page 7 register allocation map …continued Address Register name R/W Bit definition b7 28 1Ch LN3_CFG_12 R 29 1Dh LN3_CFG_13 R 31 1Fh PAGE_ADDRESS R LN3_RES2[7:0] LN3_FCHK[7:0] PAGE Default Bin Hex ...
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... Symbol Access Value Description R/W Symbol Access Value LN2_K[4:0] R/W Symbol Access Value LN2_M[7:0] R/W Symbol Access Value LN2_CS[1:0] R/W LN2_N[4:0] R/W Symbol Access Value LN2_N'[4:0] R/W Rev. 01 — 26 May 2009 DAC1408D650 Value Description Value Description Description Description Description Description © NXP B.V. 2009. All rights reserved ...
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... LN3_BID[3:0] R/W Symbol Access Value LN3_LID[4:0] R/W Symbol Access Value LN3_SCR R/W LN3_L[4:0] R/W Symbol Access Value LN3_F[7:0] R/W Symbol Access Value LN3_K[4:0] R/W Rev. 01 — 26 May 2009 DAC1408D650 Description Description Description Description Description Description Description Description Description Description Description © NXP B.V. 2009. All rights reserved ...
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... Access Value LN3_HD R/W LN3_CF[4:0] R/W Symbol Access Value LN3_RES1[7:0] R/W Symbol Access Value LN3_RES2[7:0] R/W Symbol Access Value LN3_FCHK[7:0] R/W Symbol Access Value PAGE R/W - Rev. 01 — 26 May 2009 DAC1408D650 Description Description Description Description Description Description Description Description Description page_address © NXP B.V. 2009. All rights reserved ...
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... scale (1) ( 0.20 14.1 7.1 14.1 7.1 0.5 0.09 13.9 6.1 13.9 6.1 REFERENCES JEDEC JEITA MS-026 Rev. 01 — 26 May 2009 DAC1408D650 detail 16.15 16.15 0.75 1 0.2 0.08 0.08 15.85 15.85 0.45 EUROPEAN PROJECTION SOT638 (1) ( ...
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... Local Multipoint Distribution Service Low-voltage Differential Signaling Numerically Controlled Oscillator Negative Metal-Oxide Semiconductor Phase-Locked Loop Serializer/Deserializer Spurious Free Dynamic Range Serial Peripheral Interface Wideband Code Division Multiple Access Wireless Local Loop Rev. 01 — 26 May 2009 DAC1408D650 © NXP B.V. 2009. All rights reserved ...
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... Table 184. Revision history Document ID Release date DAC1408D650_1 20090526 DAC1408D650_1 Objective data sheet Dual 14-bit DAC 650 Msps, 2 and 4 interpolating Data sheet status Change notice Objective data sheet - Rev. 01 — 26 May 2009 DAC1408D650 Supersedes - © NXP B.V. 2009. All rights reserved ...
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... Export might require a prior authorization from national authorities. 14.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. http://www.nxp.com salesaddresses@nxp.com Rev. 01 — 26 May 2009 DAC1408D650 © NXP B.V. 2009. All rights reserved ...
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... Table 54. SET_RATIO_PD1 register (address 13h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 55. SET_RATIO_PD2 (address 14h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 56. SET_RATIO_PFD register (address 15h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 57. SET_VCM_VOLTAGE register (address 16h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 58. SET_SYNC register (address 17h) Rev. 01 — 26 May 2009 DAC1408D650 continued >> © NXP B.V. 2009. All rights reserved ...
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... Table 106.ILA_MON_3_2 register (address 0Bh) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 65 Table 107.LOCK_CNT_MON_LN23 register (address 0Ch) bit description . . . . . . . . . . . . . 65 Table 108.FLAG_CNT_LSB_LN0 register (address 10h) bit description . . . . . . . . . . . . . . 65 Table 109.FLAG_CNT_MSB_LN0 register (address 11h) bit description . . . . . . . . . . . . . . 65 Table 110.FLAG_CNT_LSB_LN1 register Rev. 01 — 26 May 2009 DAC1408D650 continued >> © NXP B.V. 2009. All rights reserved ...
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... Table 159.LN2_CFG_5 register (address 05h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 76 Table 160.LN2_CFG_6 register (address 06h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 76 Table 161.LN2_CFG_7 register (address 07h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 76 Table 162.LN2_CFG_8 register (address 08h) Rev. 01 — 26 May 2009 DAC1408D650 continued >> © NXP B.V. 2009. All rights reserved ...
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... Table 181.LN3_CFG_13 register (address 1Dh) bit description . . . . . . . . . . . . . . . . . . . . . . . . .78 Table 182.PAGE_ADDRESS register (address 1Fh) bit description . . . . . . . . . . . . . . . . . . . . . . . . .78 Table 183.Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .80 Table 184.Revision history . . . . . . . . . . . . . . . . . . . . . . . .81 DAC1408D650_1 Objective data sheet Dual 14-bit DAC 650 Msps, 2 and 4 interpolating Rev. 01 — 26 May 2009 DAC1408D650 © NXP B.V. 2009. All rights reserved ...
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... AQM when using auxiliary DACs .33 i(cm) Fig 21. An example interface to a 0.5 V AQM when using auxiliary DACs .34 i(cm) Fig 22. Package outline SOT638 (HTQFP100 .79 DAC1408D650_1 Objective data sheet Dual 14-bit DAC 650 Msps, 2 and 4 interpolating Rev. 01 — 26 May 2009 DAC1408D650 © NXP B.V. 2009. All rights reserved ...
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... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com DAC1408D650 All rights reserved. Date of release: 26 May 2009 Document identifier: DAC1408D650_1 ...